62 	rk_clrsetreg(&pll->con0,  in rkclk_set_pll()
65 	rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,  in rkclk_set_pll()
86 	rk_clrsetreg(&cru->cru_mode_con,  in rkclk_init()
106 	rk_clrsetreg(&cru->cru_clksel_con[0],  in rkclk_init()
111 	rk_clrsetreg(&cru->cru_clksel_con[1],  in rkclk_init()
129 	rk_clrsetreg(&cru->cru_clksel_con[0],  in rkclk_init()
134 	rk_clrsetreg(&cru->cru_clksel_con[1],  in rkclk_init()
154 	rk_clrsetreg(&cru->cru_clksel_con[10],  in rkclk_init()
163 	rk_clrsetreg(&cru->cru_mode_con,  in rkclk_init()
263 			rk_clrsetreg(&cru->cru_clksel_con[5], CLK_MAC_DIV_MASK,  in rk322x_mac_set_clk()
296 		rk_clrsetreg(&cru->cru_clksel_con[11],  in rockchip_mmc_set_clk()
299 		rk_clrsetreg(&cru->cru_clksel_con[12],  in rockchip_mmc_set_clk()
305 		rk_clrsetreg(&cru->cru_clksel_con[11],  in rockchip_mmc_set_clk()
338 	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,  in rk322x_ddr_set_clk()
342 	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,  in rk322x_ddr_set_clk()
410 		rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), 0);  in rk322x_gmac_set_parent()
420 		rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), BIT(5));  in rk322x_gmac_set_parent()
441 		rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), 0);  in rk322x_gmac_extclk_set_parent()
445 		rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), BIT(10));  in rk322x_gmac_extclk_set_parent()