1 // SPDX-License-Identifier: GPL-2.0
7 #include <clk-uclass.h>
16 #include <dt-bindings/clock/rk3036-cru.h>
27 	((input_rate) / (output_rate) - 1);
44 static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id,  in rkclk_set_pll()  argument
48 	struct rk3036_pll *pll = &cru->pll[pll_id];  in rkclk_set_pll()
51 	uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;  in rkclk_set_pll()
52 	uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;  in rkclk_set_pll()
56 			pll, div->fbdiv, div->refdiv, div->postdiv1,  in rkclk_set_pll()
57 			div->postdiv2, vco_hz, output_hz);  in rkclk_set_pll()
62 	rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);  in rkclk_set_pll()
64 	rk_clrsetreg(&pll->con0,  in rkclk_set_pll()
66 		     (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);  in rkclk_set_pll()
67 	rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,  in rkclk_set_pll()
68 		     (div->postdiv2 << PLL_POSTDIV2_SHIFT |  in rkclk_set_pll()
69 		     div->refdiv << PLL_REFDIV_SHIFT));  in rkclk_set_pll()
72 	while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))  in rkclk_set_pll()
78 static void rkclk_init(struct rk3036_cru *cru)  in rkclk_init()  argument
84 	/* pll enter slow-mode */  in rkclk_init()
85 	rk_clrsetreg(&cru->cru_mode_con,  in rkclk_init()
91 	rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);  in rkclk_init()
92 	rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);  in rkclk_init()
99 	aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;  in rkclk_init()
102 	pclk_div = APLL_HZ / CORE_PERI_HZ - 1;  in rkclk_init()
105 	rk_clrsetreg(&cru->cru_clksel_con[0],  in rkclk_init()
110 	rk_clrsetreg(&cru->cru_clksel_con[1],  in rkclk_init()
119 	aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;  in rkclk_init()
122 	pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1;  in rkclk_init()
125 	hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1;  in rkclk_init()
128 	rk_clrsetreg(&cru->cru_clksel_con[0],  in rkclk_init()
133 	rk_clrsetreg(&cru->cru_clksel_con[1],  in rkclk_init()
142 	aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;  in rkclk_init()
153 	rk_clrsetreg(&cru->cru_clksel_con[10],  in rkclk_init()
161 	/* PLL enter normal-mode */  in rkclk_init()
162 	rk_clrsetreg(&cru->cru_mode_con,  in rkclk_init()
169 static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru,  in rkclk_pll_get_rate()  argument
175 	struct rk3036_pll *pll = &cru->pll[pll_id];  in rkclk_pll_get_rate()
187 	con = readl(&cru->cru_mode_con);  in rkclk_pll_get_rate()
197 		con = readl(&pll->con0);  in rkclk_pll_get_rate()
200 		con = readl(&pll->con1);  in rkclk_pll_get_rate()
210 static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate,  in rockchip_mmc_get_clk()  argument
220 		con = readl(&cru->cru_clksel_con[12]);  in rockchip_mmc_get_clk()
226 		con = readl(&cru->cru_clksel_con[12]);  in rockchip_mmc_get_clk()
231 		return -EINVAL;  in rockchip_mmc_get_clk()
238 static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,  in rockchip_mmc_set_clk()  argument
251 		assert(src_clk_div - 1 < 128);  in rockchip_mmc_set_clk()
260 		rk_clrsetreg(&cru->cru_clksel_con[12],  in rockchip_mmc_set_clk()
263 			     (src_clk_div - 1) << EMMC_DIV_SHIFT);  in rockchip_mmc_set_clk()
267 		rk_clrsetreg(&cru->cru_clksel_con[11],  in rockchip_mmc_set_clk()
270 			     (src_clk_div - 1) << MMC0_DIV_SHIFT);  in rockchip_mmc_set_clk()
273 		return -EINVAL;  in rockchip_mmc_set_clk()
276 	return rockchip_mmc_get_clk(cru, clk_general_rate, periph);  in rockchip_mmc_set_clk()
281 	struct rk3036_clk_priv *priv = dev_get_priv(clk->dev);  in rk3036_clk_get_rate()
283 	switch (clk->id) {  in rk3036_clk_get_rate()
285 		return rkclk_pll_get_rate(priv->cru, clk->id);  in rk3036_clk_get_rate()
287 		return -ENOENT;  in rk3036_clk_get_rate()
293 	struct rk3036_clk_priv *priv = dev_get_priv(clk->dev);  in rk3036_clk_set_rate()
296 	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);  in rk3036_clk_set_rate()
297 	switch (clk->id) {  in rk3036_clk_set_rate()
302 		new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,  in rk3036_clk_set_rate()
303 						clk->id, rate);  in rk3036_clk_set_rate()
306 		return -ENOENT;  in rk3036_clk_set_rate()
321 	priv->cru = dev_read_addr_ptr(dev);  in rk3036_clk_ofdata_to_platdata()
330 	rkclk_init(priv->cru);  in rk3036_clk_probe()
348 		priv->glb_srst_fst_value = offsetof(struct rk3036_cru,  in rk3036_clk_bind()
350 		priv->glb_srst_snd_value = offsetof(struct rk3036_cru,  in rk3036_clk_bind()
352 		sys_child->priv = priv;  in rk3036_clk_bind()
366 	{ .compatible = "rockchip,rk3036-cru" },