55 	case IMX8QXP_A35_DIV:  in imx8_clk_get_rate()
59 	case IMX8QXP_I2C0_CLK:  in imx8_clk_get_rate()
63 	case IMX8QXP_I2C1_CLK:  in imx8_clk_get_rate()
67 	case IMX8QXP_I2C2_CLK:  in imx8_clk_get_rate()
71 	case IMX8QXP_I2C3_CLK:  in imx8_clk_get_rate()
75 	case IMX8QXP_SDHC0_IPG_CLK:  in imx8_clk_get_rate()
76 	case IMX8QXP_SDHC0_CLK:  in imx8_clk_get_rate()
77 	case IMX8QXP_SDHC0_DIV:  in imx8_clk_get_rate()
81 	case IMX8QXP_SDHC1_IPG_CLK:  in imx8_clk_get_rate()
82 	case IMX8QXP_SDHC1_CLK:  in imx8_clk_get_rate()
83 	case IMX8QXP_SDHC1_DIV:  in imx8_clk_get_rate()
87 	case IMX8QXP_UART0_IPG_CLK:  in imx8_clk_get_rate()
88 	case IMX8QXP_UART0_CLK:  in imx8_clk_get_rate()
92 	case IMX8QXP_UART1_CLK:  in imx8_clk_get_rate()
96 	case IMX8QXP_UART2_CLK:  in imx8_clk_get_rate()
100 	case IMX8QXP_UART3_CLK:  in imx8_clk_get_rate()
104 	case IMX8QXP_ENET0_IPG_CLK:  in imx8_clk_get_rate()
105 	case IMX8QXP_ENET0_AHB_CLK:  in imx8_clk_get_rate()
106 	case IMX8QXP_ENET0_REF_DIV:  in imx8_clk_get_rate()
107 	case IMX8QXP_ENET0_PTP_CLK:  in imx8_clk_get_rate()
111 	case IMX8QXP_ENET1_IPG_CLK:  in imx8_clk_get_rate()
112 	case IMX8QXP_ENET1_AHB_CLK:  in imx8_clk_get_rate()
113 	case IMX8QXP_ENET1_REF_DIV:  in imx8_clk_get_rate()
114 	case IMX8QXP_ENET1_PTP_CLK:  in imx8_clk_get_rate()
148 	case IMX8QXP_I2C0_CLK:  in imx8_clk_set_rate()
152 	case IMX8QXP_I2C1_CLK:  in imx8_clk_set_rate()
156 	case IMX8QXP_I2C2_CLK:  in imx8_clk_set_rate()
160 	case IMX8QXP_I2C3_CLK:  in imx8_clk_set_rate()
164 	case IMX8QXP_UART0_CLK:  in imx8_clk_set_rate()
168 	case IMX8QXP_UART1_CLK:  in imx8_clk_set_rate()
172 	case IMX8QXP_UART2_CLK:  in imx8_clk_set_rate()
176 	case IMX8QXP_UART3_CLK:  in imx8_clk_set_rate()
180 	case IMX8QXP_SDHC0_IPG_CLK:  in imx8_clk_set_rate()
181 	case IMX8QXP_SDHC0_CLK:  in imx8_clk_set_rate()
182 	case IMX8QXP_SDHC0_DIV:  in imx8_clk_set_rate()
186 	case IMX8QXP_SDHC1_SEL:  in imx8_clk_set_rate()
187 	case IMX8QXP_SDHC0_SEL:  in imx8_clk_set_rate()
189 	case IMX8QXP_SDHC1_IPG_CLK:  in imx8_clk_set_rate()
190 	case IMX8QXP_SDHC1_CLK:  in imx8_clk_set_rate()
191 	case IMX8QXP_SDHC1_DIV:  in imx8_clk_set_rate()
195 	case IMX8QXP_ENET0_IPG_CLK:  in imx8_clk_set_rate()
196 	case IMX8QXP_ENET0_AHB_CLK:  in imx8_clk_set_rate()
197 	case IMX8QXP_ENET0_REF_DIV:  in imx8_clk_set_rate()
198 	case IMX8QXP_ENET0_PTP_CLK:  in imx8_clk_set_rate()
202 	case IMX8QXP_ENET1_IPG_CLK:  in imx8_clk_set_rate()
203 	case IMX8QXP_ENET1_AHB_CLK:  in imx8_clk_set_rate()
204 	case IMX8QXP_ENET1_REF_DIV:  in imx8_clk_set_rate()
205 	case IMX8QXP_ENET1_PTP_CLK:  in imx8_clk_set_rate()
237 	case IMX8QXP_I2C0_CLK:  in __imx8_clk_enable()
241 	case IMX8QXP_I2C1_CLK:  in __imx8_clk_enable()
245 	case IMX8QXP_I2C2_CLK:  in __imx8_clk_enable()
249 	case IMX8QXP_I2C3_CLK:  in __imx8_clk_enable()
253 	case IMX8QXP_UART0_CLK:  in __imx8_clk_enable()
257 	case IMX8QXP_UART1_CLK:  in __imx8_clk_enable()
261 	case IMX8QXP_UART2_CLK:  in __imx8_clk_enable()
265 	case IMX8QXP_UART3_CLK:  in __imx8_clk_enable()
269 	case IMX8QXP_SDHC0_IPG_CLK:  in __imx8_clk_enable()
270 	case IMX8QXP_SDHC0_CLK:  in __imx8_clk_enable()
271 	case IMX8QXP_SDHC0_DIV:  in __imx8_clk_enable()
275 	case IMX8QXP_SDHC1_IPG_CLK:  in __imx8_clk_enable()
276 	case IMX8QXP_SDHC1_CLK:  in __imx8_clk_enable()
277 	case IMX8QXP_SDHC1_DIV:  in __imx8_clk_enable()
281 	case IMX8QXP_ENET0_IPG_CLK:  in __imx8_clk_enable()
282 	case IMX8QXP_ENET0_AHB_CLK:  in __imx8_clk_enable()
283 	case IMX8QXP_ENET0_REF_DIV:  in __imx8_clk_enable()
284 	case IMX8QXP_ENET0_PTP_CLK:  in __imx8_clk_enable()
288 	case IMX8QXP_ENET1_IPG_CLK:  in __imx8_clk_enable()
289 	case IMX8QXP_ENET1_AHB_CLK:  in __imx8_clk_enable()
290 	case IMX8QXP_ENET1_REF_DIV:  in __imx8_clk_enable()
291 	case IMX8QXP_ENET1_PTP_CLK:  in __imx8_clk_enable()