Lines Matching +full:csi +full:- +full:aclk
1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
7 #include <clk-uclass.h>
15 #include <dt-bindings/clock/stm32mp1-clks.h>
16 #include <dt-bindings/clock/stm32mp1-clksrc.h>
674 [_CSI] = "CSI",
694 [_ACLK] = "ACLK",
745 (u32)priv->osc[idx], priv->osc[idx] / 1000); in stm32mp1_clk_get_fixed()
747 return priv->osc[idx]; in stm32mp1_clk_get_fixed()
752 const struct stm32mp1_clk_gate *gate = priv->data->gate; in stm32mp1_clk_get_id()
753 int i, nb_clks = priv->data->nb_gate; in stm32mp1_clk_get_id()
762 return -EINVAL; in stm32mp1_clk_get_id()
771 const struct stm32mp1_clk_gate *gate = priv->data->gate; in stm32mp1_clk_get_sel()
776 return -EINVAL; in stm32mp1_clk_get_sel()
785 const struct stm32mp1_clk_gate *gate = priv->data->gate; in stm32mp1_clk_get_fixed_parent()
788 return -ENOENT; in stm32mp1_clk_get_fixed_parent()
796 const struct stm32mp1_clk_sel *sel = priv->data->sel; in stm32mp1_clk_get_parent()
816 p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk; in stm32mp1_clk_get_parent()
831 return -EINVAL; in stm32mp1_clk_get_parent()
837 const struct stm32mp1_clk_pll *pll = priv->data->pll; in pll_get_fref_ck()
843 selr = readl(priv->base + pll[pll_id].rckxselr); in pll_get_fref_ck()
855 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
856 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1)
862 const struct stm32mp1_clk_pll *pll = priv->data->pll; in pll_get_fvco()
867 cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1); in pll_get_fvco()
868 fracr = readl(priv->base + pll[pll_id].pllxfracr); in pll_get_fvco()
900 const struct stm32mp1_clk_pll *pll = priv->data->pll; in stm32mp1_read_pll_freq()
909 cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2); in stm32mp1_read_pll_freq()
928 reg = readl(priv->base + RCC_MPCKSELR); in stm32mp1_clk_get()
940 reg = readl(priv->base + RCC_MPCKDIVR); in stm32mp1_clk_get()
953 reg = readl(priv->base + RCC_ASSCKSELR); in stm32mp1_clk_get()
967 reg = readl(priv->base + RCC_AXIDIVR); in stm32mp1_clk_get()
972 reg = readl(priv->base + RCC_APB4DIVR); in stm32mp1_clk_get()
976 reg = readl(priv->base + RCC_APB5DIVR); in stm32mp1_clk_get()
988 reg = readl(priv->base + RCC_MSSCKSELR); in stm32mp1_clk_get()
1005 reg = readl(priv->base + RCC_MCUDIVR); in stm32mp1_clk_get()
1010 reg = readl(priv->base + RCC_APB1DIVR); in stm32mp1_clk_get()
1014 reg = readl(priv->base + RCC_APB2DIVR); in stm32mp1_clk_get()
1018 reg = readl(priv->base + RCC_APB3DIVR); in stm32mp1_clk_get()
1027 reg = readl(priv->base + RCC_CPERCKSELR); in stm32mp1_clk_get()
1065 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P); in stm32mp1_clk_get()
1070 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P); in stm32mp1_clk_get()
1075 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P); in stm32mp1_clk_get()
1080 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P); in stm32mp1_clk_get()
1114 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev); in stm32mp1_clk_enable()
1115 const struct stm32mp1_clk_gate *gate = priv->data->gate; in stm32mp1_clk_enable()
1116 int i = stm32mp1_clk_get_id(priv, clk->id); in stm32mp1_clk_enable()
1122 writel(BIT(gate[i].bit), priv->base + gate[i].offset); in stm32mp1_clk_enable()
1124 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit)); in stm32mp1_clk_enable()
1126 debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id); in stm32mp1_clk_enable()
1133 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev); in stm32mp1_clk_disable()
1134 const struct stm32mp1_clk_gate *gate = priv->data->gate; in stm32mp1_clk_disable()
1135 int i = stm32mp1_clk_get_id(priv, clk->id); in stm32mp1_clk_disable()
1142 priv->base + gate[i].offset in stm32mp1_clk_disable()
1145 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit)); in stm32mp1_clk_disable()
1147 debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id); in stm32mp1_clk_disable()
1154 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev); in stm32mp1_clk_get_rate()
1155 int p = stm32mp1_clk_get_parent(priv, clk->id); in stm32mp1_clk_get_rate()
1165 __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]); in stm32mp1_clk_get_rate()
1222 * to "medium low drive", and vice-versa. in stm32mp1_lse_enable()
1229 value--; in stm32mp1_lse_enable()
1309 pr_err("clk-hsi frequency invalid"); in stm32mp1_hsidiv()
1310 return -1; in stm32mp1_hsidiv()
1321 const struct stm32mp1_clk_pll *pll = priv->data->pll; in pll_start()
1323 clrsetbits_le32(priv->base + pll[pll_id].pllxcr, in pll_start()
1331 const struct stm32mp1_clk_pll *pll = priv->data->pll; in pll_output()
1332 u32 pllxcr = priv->base + pll[pll_id].pllxcr; in pll_output()
1353 const struct stm32mp1_clk_pll *pll = priv->data->pll; in pll_stop()
1354 u32 pllxcr = priv->base + pll[pll_id].pllxcr; in pll_stop()
1372 const struct stm32mp1_clk_pll *pll = priv->data->pll; in pll_config_output()
1373 fdt_addr_t rcc = priv->base; in pll_config_output()
1388 const struct stm32mp1_clk_pll *pll = priv->data->pll; in pll_config()
1389 fdt_addr_t rcc = priv->base; in pll_config()
1396 src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK; in pll_config()
1404 return -EINVAL; in pll_config()
1417 /* fractional configuration: load sigma-delta modulator (SDM) */ in pll_config()
1434 const struct stm32mp1_clk_pll *pll = priv->data->pll; in pll_csg()
1444 writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr); in pll_csg()
1446 setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL); in pll_csg()
1451 u32 address = priv->base + (clksrc >> 4); in set_clksrc()
1492 /* need to update gd->arch.timer_rate_hz with new frequency */ in stgen_config()
1494 pr_debug("gd->arch.timer_rate_hz = %x\n", in stgen_config()
1495 (u32)gd->arch.timer_rate_hz); in stgen_config()
1518 u32 address = priv->base + (clksrc >> 4); in stm32mp1_mco_csg()
1521 * binding clksrc : bit15-4 offset in stm32mp1_mco_csg()
1523 * bit2-0: MCOSEL[2:0] in stm32mp1_mco_csg()
1542 u32 address = priv->base + RCC_BDCR; in set_rtcsrc()
1563 u32 address = priv->base + ((pkcs >> 4) & 0xFFF); in pkcs_config()
1577 fdt_addr_t rcc = priv->base; in stm32mp1_clktree()
1591 return -FDT_ERR_NOTFOUND; in stm32mp1_clktree()
1597 return -FDT_ERR_NOTFOUND; in stm32mp1_clktree()
1612 return -FDT_ERR_NOTFOUND; in stm32mp1_clktree()
1622 * switch ON oscillator found in device-tree, in stm32mp1_clktree()
1625 if (priv->osc[_LSI]) in stm32mp1_clktree()
1628 if (priv->osc[_LSE]) { in stm32mp1_clktree()
1630 struct udevice *dev = priv->osc_dev[_LSE]; in stm32mp1_clktree()
1641 if (priv->osc[_HSE]) { in stm32mp1_clktree()
1643 struct udevice *dev = priv->osc_dev[_HSE]; in stm32mp1_clktree()
1651 /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) in stm32mp1_clktree()
1652 * => switch on CSI even if node is not present in device tree in stm32mp1_clktree()
1668 if (priv->osc[_HSI]) { in stm32mp1_clktree()
1669 stm32mp1_hsidiv(rcc, priv->osc[_HSI]); in stm32mp1_clktree()
1710 } else if (ret != -FDT_ERR_NOTFOUND) { in stm32mp1_clktree()
1726 if (priv->osc[_LSE]) in stm32mp1_clktree()
1752 * (FMC-NAND / QPSI-NOR) and switching source is allowed in stm32mp1_clktree()
1764 /* switch OFF HSI if not found in device-tree */ in stm32mp1_clktree()
1765 if (!priv->osc[_HSI]) in stm32mp1_clktree()
1768 /* Software Self-Refresh mode (SSR) during DDR initilialization */ in stm32mp1_clktree()
1769 clrsetbits_le32(priv->base + RCC_DDRITFCR, in stm32mp1_clktree()
1784 const struct stm32mp1_clk_pll *pll = priv->data->pll; in pll_set_output_rate()
1785 u32 pllxcr = priv->base + pll[pll_id].pllxcr; in pll_set_output_rate()
1790 return -EINVAL; in pll_set_output_rate()
1806 clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2, in pll_set_output_rate()
1808 (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id)); in pll_set_output_rate()
1817 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev); in stm32mp1_clk_set_rate()
1820 switch (clk->id) { in stm32mp1_clk_set_rate()
1826 return -EINVAL; in stm32mp1_clk_set_rate()
1829 p = stm32mp1_clk_get_parent(priv, clk->id); in stm32mp1_clk_set_rate()
1831 return -EINVAL; in stm32mp1_clk_set_rate()
1836 return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate); in stm32mp1_clk_set_rate()
1839 return -EINVAL; in stm32mp1_clk_set_rate()
1849 priv->osc[index] = 0; in stm32mp1_osc_clk_init()
1855 priv->osc[index] = clk_get_rate(&clk); in stm32mp1_osc_clk_init()
1857 priv->osc_dev[index] = dev; in stm32mp1_osc_clk_init()
1865 [_LSI] = "clk-lsi", in stm32mp1_osc_init()
1866 [_LSE] = "clk-lse", in stm32mp1_osc_init()
1867 [_HSI] = "clk-hsi", in stm32mp1_osc_init()
1868 [_HSE] = "clk-hse", in stm32mp1_osc_init()
1869 [_CSI] = "clk-csi", in stm32mp1_osc_init()
1875 debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]); in stm32mp1_osc_init()
1886 printf("- %s : %s MHz\n", in stm32mp1_clk_dump()
1892 p = (readl(priv->base + priv->data->sel[i].offset) >> in stm32mp1_clk_dump()
1893 priv->data->sel[i].src) & priv->data->sel[i].msk; in stm32mp1_clk_dump()
1894 if (p < priv->data->sel[i].nb_parent) { in stm32mp1_clk_dump()
1895 s = priv->data->sel[i].parent[p]; in stm32mp1_clk_dump()
1896 printf("- %s(%d) => parent %s(%d)\n", in stm32mp1_clk_dump()
1900 printf("- %s(%d) => parent index %d is invalid\n", in stm32mp1_clk_dump()
1932 priv->base = dev_read_addr(dev->parent); in stm32mp1_clk_probe()
1933 if (priv->base == FDT_ADDR_T_NONE) in stm32mp1_clk_probe()
1934 return -EINVAL; in stm32mp1_clk_probe()
1936 priv->data = (void *)&stm32mp1_data; in stm32mp1_clk_probe()
1938 if (!priv->data->gate || !priv->data->sel || in stm32mp1_clk_probe()
1939 !priv->data->pll) in stm32mp1_clk_probe()
1940 return -EINVAL; in stm32mp1_clk_probe()
1946 if (!(gd->flags & GD_FLG_RELOC)) in stm32mp1_clk_probe()
1953 if (gd->flags & GD_FLG_RELOC) in stm32mp1_clk_probe()
1958 if (gd->flags & GD_FLG_RELOC) { in stm32mp1_clk_probe()
1962 printf("- MPU : %s MHz\n", in stm32mp1_clk_probe()
1964 printf("- MCU : %s MHz\n", in stm32mp1_clk_probe()
1966 printf("- AXI : %s MHz\n", in stm32mp1_clk_probe()
1968 printf("- PER : %s MHz\n", in stm32mp1_clk_probe()
1971 printf("- DDR : %s MHz\n", in stm32mp1_clk_probe()