37  * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1)
64 	u32 clkin = ast2500_get_clkin(scu);  in ast2500_get_mpll_rate()  local
73 	return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);  in ast2500_get_mpll_rate()
82 	u32 clkin = ast2500_get_clkin(scu);  in ast2500_get_hpll_rate()  local
85 	/* F = clkin * [(M+1) / (N+1)] / (P + 1) */  in ast2500_get_hpll_rate()
92 	return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);  in ast2500_get_hpll_rate()
101 	u32 clkin = ast2500_get_clkin(scu);  in ast2500_get_dpll_rate()  local
104 	/* F = clkin * [(M+1) / (N+1)] / (P + 1)/ (od + 1) */  in ast2500_get_dpll_rate()
109 	return (((clkin * ((num + 1) / (denum + 1))) / (post_div + 1))/ (od_div + 1));  in ast2500_get_dpll_rate()
118 	u32 clkin = ast2500_get_clkin(scu);  in ast2500_get_d2pll_rate()  local
121 	/* F = clkin * [(M+1) / (N+1)] / (P + 1)/ (od + 1) */  in ast2500_get_d2pll_rate()
127 	return (((clkin * ((num + 1) / (denum + 1))) / (post_div + 1))/ (od_div + 1));  in ast2500_get_d2pll_rate()
159 	u32 clkin = ast2500_get_hpll_rate(scu);  in ast2500_get_sdio_clk_rate()  local
165 	return (clkin / div);  in ast2500_get_sdio_clk_rate()
172 	 * especially when CLKIN = 25 MHz. The settings are in  in ast2500_get_uart_clk_rate()
175 	 * This has only been tested with default settings and CLKIN = 24 MHz.  in ast2500_get_uart_clk_rate()
331 	ulong clkin = ast2500_get_clkin(scu);  in ast2500_configure_ddr()  local
339 	ast2500_calc_clock_config(clkin, rate, &div_cfg);  in ast2500_configure_ddr()
370 	ulong clkin = ast2500_get_clkin(scu);  in ast2500_configure_d2pll()  local
384 	new_rate = ast2500_calc_clock_config(clkin, rate, &div_cfg);  in ast2500_configure_d2pll()