Lines Matching +full:g4 +full:- +full:scu
1 // SPDX-License-Identifier: GPL-2.0
7 #include <clk-uclass.h>
12 #include <dt-bindings/clock/ast2400-clock.h>
13 #include <dt-bindings/reset/ast2400-reset.h>
19 * For H-PLL and M-PLL the formula is
21 * M - Numerator
22 * N - Denumerator
23 * P - Post Divider
26 * D-PLL and D2-PLL have extra divider (OD + 1), which is not
37 extern u32 ast2400_get_clkin(struct ast2400_scu *scu) in ast2400_get_clkin() argument
40 u32 strap = readl(&scu->hwstrap); in ast2400_get_clkin()
58 * Get the rate of the M-PLL clock from input clock frequency and
59 * the value of the M-PLL Parameter Register.
61 extern u32 ast2400_get_mpll_rate(struct ast2400_scu *scu) in ast2400_get_mpll_rate() argument
64 u32 clkin = ast2400_get_clkin(scu); in ast2400_get_mpll_rate()
65 u32 mpll_reg = readl(&scu->m_pll_param); in ast2400_get_mpll_rate()
77 //mpll = 24MHz * (2-OD) * ((Numerator+2)/(Denumerator+1)) in ast2400_get_mpll_rate()
78 mult = (2 - od) * (n + 2); in ast2400_get_mpll_rate()
88 * Get the rate of the H-PLL clock from input clock frequency and
89 * the value of the H-PLL Parameter Register.
91 extern u32 ast2400_get_hpll_rate(struct ast2400_scu *scu) in ast2400_get_hpll_rate() argument
94 u32 clkin = ast2400_get_clkin(scu); in ast2400_get_hpll_rate()
95 u32 hpll_reg = readl(&scu->h_pll_param); in ast2400_get_hpll_rate()
107 /* F = 24Mhz * (2-OD) * [(N + 2) / (D + 1)] */ in ast2400_get_hpll_rate()
112 mult = (2 - od) * (n + 2); in ast2400_get_hpll_rate()
139 * Get the rate of the D2-PLL clock from input clock frequency and
140 * the value of the D2-PLL Parameter Register.
142 extern u32 ast2400_get_d2pll_rate(struct ast2400_scu *scu) in ast2400_get_d2pll_rate() argument
145 u32 clkin = ast2400_get_clkin(scu); in ast2400_get_d2pll_rate()
146 u32 d2pll_reg = readl(&scu->d2_pll_param); in ast2400_get_d2pll_rate()
159 o = (1 << (o - 1)); in ast2400_get_d2pll_rate()
177 static u32 ast2400_get_hclk(struct ast2400_scu *scu) in ast2400_get_hclk() argument
180 u32 strap = readl(&scu->hwstrap); in ast2400_get_hclk()
181 u32 rate = ast2400_get_hpll_rate(scu); in ast2400_get_hclk()
188 static u32 ast2400_get_pclk(struct ast2400_scu *scu) in ast2400_get_pclk() argument
191 rate = ast2400_get_hpll_rate(scu); in ast2400_get_pclk()
192 u32 apb_div = (readl(&scu->clk_sel1) >> 23) & 0x7; in ast2400_get_pclk()
199 static u32 ast2400_get_sdio_clk_rate(struct ast2400_scu *scu) in ast2400_get_sdio_clk_rate() argument
201 u32 clkin = ast2400_get_hpll_rate(scu); in ast2400_get_sdio_clk_rate()
202 u32 clk_sel = readl(&scu->clk_sel1); in ast2400_get_sdio_clk_rate()
210 static u32 ast2400_get_uart_clk_rate(struct ast2400_scu *scu, int uart_idx) in ast2400_get_uart_clk_rate() argument
214 if (readl(&scu->misc_ctrl1) & SCU_MISC_UARTCLK_DIV13) in ast2400_get_uart_clk_rate()
222 struct ast2400_clk_priv *priv = dev_get_priv(clk->dev); in ast2400_clk_get_rate()
225 switch (clk->id) { in ast2400_clk_get_rate()
227 rate = ast2400_get_hpll_rate(priv->scu); in ast2400_clk_get_rate()
230 rate = ast2400_get_mpll_rate(priv->scu); in ast2400_clk_get_rate()
233 rate = ast2400_get_d2pll_rate(priv->scu); in ast2400_clk_get_rate()
236 rate = ast2400_get_hclk(priv->scu); in ast2400_clk_get_rate()
239 rate = ast2400_get_pclk(priv->scu); in ast2400_clk_get_rate()
242 rate = ast2400_get_uart_clk_rate(priv->scu, 1); in ast2400_clk_get_rate()
245 rate = ast2400_get_uart_clk_rate(priv->scu, 2); in ast2400_clk_get_rate()
248 rate = ast2400_get_uart_clk_rate(priv->scu, 3); in ast2400_clk_get_rate()
251 rate = ast2400_get_uart_clk_rate(priv->scu, 4); in ast2400_clk_get_rate()
254 rate = ast2400_get_uart_clk_rate(priv->scu, 5); in ast2400_clk_get_rate()
257 rate = ast2400_get_sdio_clk_rate(priv->scu); in ast2400_clk_get_rate()
261 return -ENOENT; in ast2400_clk_get_rate()
287 if (default_cfg->input_rate == input_rate && in ast2400_get_clock_config_default()
288 default_cfg->rate == requested_rate) { in ast2400_get_clock_config_default()
289 *cfg = default_cfg->cfg; in ast2400_get_clock_config_default()
298 * @input_rate - the rate of input clock in Hz
299 * @requested_rate - desired output rate in Hz
300 * @div - this is an IN/OUT parameter, at input all fields of the config
343 if (new_rate_khz - rate_khz < delta) { in ast2400_calc_clock_config()
344 delta = new_rate_khz - rate_khz; in ast2400_calc_clock_config()
355 static ulong ast2400_configure_ddr(struct ast2400_scu *scu, ulong rate) in ast2400_configure_ddr() argument
357 ulong clkin = ast2400_get_clkin(scu); in ast2400_configure_ddr()
367 mpll_reg = readl(&scu->m_pll_param); in ast2400_configure_ddr()
374 writel(mpll_reg, &scu->m_pll_param); in ast2400_configure_ddr()
376 return ast2400_get_mpll_rate(scu); in ast2400_configure_ddr()
381 struct ast2400_clk_priv *priv = dev_get_priv(clk->dev); in ast2400_clk_set_rate()
384 switch (clk->id) { in ast2400_clk_set_rate()
387 new_rate = ast2400_configure_ddr(priv->scu, rate); in ast2400_clk_set_rate()
390 return -ENOENT; in ast2400_clk_set_rate()
399 static ulong ast2400_configure_mac(struct ast2400_scu *scu, int index) in ast2400_configure_mac() argument
414 return -EINVAL; in ast2400_configure_mac()
418 * Disable MAC, start its clock and re-enable it. in ast2400_configure_mac()
422 setbits_le32(&scu->sysreset_ctrl1, reset_bit); in ast2400_configure_mac()
424 clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit); in ast2400_configure_mac()
426 clrbits_le32(&scu->sysreset_ctrl1, reset_bit); in ast2400_configure_mac()
432 static ulong ast2400_enable_sdclk(struct ast2400_scu *scu) in ast2400_enable_sdclk() argument
440 setbits_le32(&scu->sysreset_ctrl1, reset_bit); in ast2400_enable_sdclk()
443 clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit); in ast2400_enable_sdclk()
445 clrbits_le32(&scu->sysreset_ctrl1, reset_bit); in ast2400_enable_sdclk()
454 static ulong ast2400_enable_extsdclk(struct ast2400_scu *scu) in ast2400_enable_extsdclk() argument
456 u32 clk_sel = readl(&scu->clk_sel1); in ast2400_enable_extsdclk()
461 // SDCLK = G4 H-PLL / 4, G5 = H-PLL /8 in ast2400_enable_extsdclk()
464 writel(clk_sel, &scu->clk_sel1); in ast2400_enable_extsdclk()
467 setbits_le32(&scu->clk_sel1, enableclk_bit); in ast2400_enable_extsdclk()
474 struct ast2400_clk_priv *priv = dev_get_priv(clk->dev); in ast2400_clk_enable()
476 switch (clk->id) { in ast2400_clk_enable()
478 ast2400_configure_mac(priv->scu, 1); in ast2400_clk_enable()
481 ast2400_configure_mac(priv->scu, 2); in ast2400_clk_enable()
484 ast2400_enable_sdclk(priv->scu); in ast2400_clk_enable()
487 ast2400_enable_extsdclk(priv->scu); in ast2400_clk_enable()
491 return -ENOENT; in ast2400_clk_enable()
508 priv->scu = devfdt_get_addr_ptr(dev); in ast2400_clk_probe()
509 if (IS_ERR(priv->scu)) in ast2400_clk_probe()
510 return PTR_ERR(priv->scu); in ast2400_clk_probe()
520 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); in ast2400_clk_bind()
569 if (ret == -ENOTSUPP) { in soc_clk_dump()
589 { .compatible = "aspeed,ast2400-scu" },