Lines Matching refs:SATAHC_BASE
45 #define SATAHC_BASE KW_SATA_BASE macro
48 #define SATAHC_BASE MVEBU_AXP_SATA_BASE macro
51 #define SATA0_BASE (SATAHC_BASE + 0x2000)
52 #define SATA1_BASE (SATAHC_BASE + 0x4000)
323 tmp = in_le32(SATAHC_BASE + SATAHC_ICR); in mv_start_edma_engine()
325 out_le32(SATAHC_BASE + SATAHC_ICR, tmp); in mv_start_edma_engine()
390 out_le32(SATAHC_BASE + SATAHC_ICT, 0x00); in mv_reset_one_hc()
391 out_le32(SATAHC_BASE + SATAHC_ITT, 0x00); in mv_reset_one_hc()
392 out_le32(SATAHC_BASE + SATAHC_ICR, 0x00); in mv_reset_one_hc()
533 res = ata_wait_register((u32 *)(SATAHC_BASE + SATAHC_ICR), tmp, in wait_dma_completion()
550 tmp = in_le32(SATAHC_BASE + SATAHC_ICR); in process_responses()
556 out_le32(SATAHC_BASE + SATAHC_ICR, tmp); in process_responses()