6  * Originally based on the Linux kernel v4.18 drivers/iio/adc/stm32-adc.c.
10 #include <adc.h>
13 #include "stm32-adc-core.h"
15 /* STM32H7 - Registers for each ADC instance */
46 /* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */
66 	struct stm32_adc *adc = dev_get_priv(dev);  in stm32_adc_stop()  local
68 	setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADDIS);  in stm32_adc_stop()
69 	clrbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_BOOST);  in stm32_adc_stop()
70 	/* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */  in stm32_adc_stop()
71 	setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_DEEPPWD);  in stm32_adc_stop()
72 	adc->active_channel = -1;  in stm32_adc_stop()
81 	struct stm32_adc *adc = dev_get_priv(dev);  in stm32_adc_start_channel()  local
85 	/* Exit deep power down, then enable ADC voltage regulator */  in stm32_adc_start_channel()
86 	clrbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_DEEPPWD);  in stm32_adc_start_channel()
87 	setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADVREGEN);  in stm32_adc_start_channel()
89 		setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_BOOST);  in stm32_adc_start_channel()
92 	if (!adc->cfg->has_vregready) {  in stm32_adc_start_channel()
95 		ret = readl_poll_timeout(adc->regs + STM32H7_ADC_ISR, val,  in stm32_adc_start_channel()
106 	writel(0, adc->regs + STM32H7_ADC_DIFSEL);  in stm32_adc_start_channel()
108 	/* Enable ADC, Poll for ADRDY to be set (after adc startup time) */  in stm32_adc_start_channel()
109 	setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADEN);  in stm32_adc_start_channel()
110 	ret = readl_poll_timeout(adc->regs + STM32H7_ADC_ISR, val,  in stm32_adc_start_channel()
114 		dev_err(dev, "Failed to enable ADC: %d\n", ret);  in stm32_adc_start_channel()
119 	writel(uc_pdata->channel_mask, adc->regs + STM32H7_ADC_PCSEL);  in stm32_adc_start_channel()
122 	writel(0xffffffff, adc->regs + STM32H7_ADC_SMPR1);  in stm32_adc_start_channel()
123 	writel(0xffffffff, adc->regs + STM32H7_ADC_SMPR2);  in stm32_adc_start_channel()
126 	writel(channel << STM32H7_SQ1_SHIFT, adc->regs + STM32H7_ADC_SQR1);  in stm32_adc_start_channel()
129 	clrbits_le32(adc->regs + STM32H7_ADC_CFGR, STM32H7_EXTEN |  in stm32_adc_start_channel()
131 	adc->active_channel = channel;  in stm32_adc_start_channel()
139 	struct stm32_adc *adc = dev_get_priv(dev);  in stm32_adc_channel_data()  local
143 	if (channel != adc->active_channel) {  in stm32_adc_channel_data()
148 	setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADSTART);  in stm32_adc_channel_data()
149 	ret = readl_poll_timeout(adc->regs + STM32H7_ADC_ISR, val,  in stm32_adc_channel_data()
156 	*data = readl(adc->regs + STM32H7_ADC_DR);  in stm32_adc_channel_data()
164 	struct stm32_adc *adc = dev_get_priv(dev);  in stm32_adc_chan_of_init()  local
169 	num_channels = dev_read_size(dev, "st,adc-channels");  in stm32_adc_chan_of_init()
171 		dev_err(dev, "can't get st,adc-channels: %d\n", num_channels);  in stm32_adc_chan_of_init()
176 	if (num_channels > adc->cfg->max_channels) {  in stm32_adc_chan_of_init()
177 		dev_err(dev, "too many st,adc-channels: %d\n", num_channels);  in stm32_adc_chan_of_init()
181 	ret = dev_read_u32_array(dev, "st,adc-channels", chans, num_channels);  in stm32_adc_chan_of_init()
183 		dev_err(dev, "can't read st,adc-channels: %d\n", ret);  in stm32_adc_chan_of_init()
188 		if (chans[i] >= adc->cfg->max_channels) {  in stm32_adc_chan_of_init()
195 	uc_pdata->data_mask = (1 << adc->cfg->num_bits) - 1;  in stm32_adc_chan_of_init()
206 	struct stm32_adc *adc = dev_get_priv(dev);  in stm32_adc_probe()  local
214 	adc->regs = common->base + offset;  in stm32_adc_probe()
215 	adc->cfg = (const struct stm32_adc_cfg *)dev_get_driver_data(dev);  in stm32_adc_probe()
243 	{ .compatible = "st,stm32h7-adc",
245 	{ .compatible = "st,stm32mp1-adc",
251 	.name  = "stm32-adc",