1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
6  * Originally based on the Linux kernel v4.18 drivers/iio/adc/stm32-adc-core.c.
12 #include "stm32-adc-core.h"
14 /* STM32H7 - common registers for all ADC instances */
17 /* STM32H7_ADC_CCR - bit fields */
27  * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
66 	if (!clk_valid(&common->bclk)) {  in stm32h7_adc_clk_sel()
67 		dev_err(dev, "No bclk clock found\n");  in stm32h7_adc_clk_sel()
68 		return -ENOENT;  in stm32h7_adc_clk_sel()
76 	if (clk_valid(&common->aclk)) {  in stm32h7_adc_clk_sel()
81 		rate = clk_get_rate(&common->aclk);  in stm32h7_adc_clk_sel()
83 			dev_err(dev, "Invalid aclk rate: 0\n");  in stm32h7_adc_clk_sel()
84 			return -EINVAL;  in stm32h7_adc_clk_sel()
101 	rate = clk_get_rate(&common->bclk);  in stm32h7_adc_clk_sel()
103 		dev_err(dev, "Invalid bus clock rate: 0\n");  in stm32h7_adc_clk_sel()
104 		return -EINVAL;  in stm32h7_adc_clk_sel()
119 	dev_err(dev, "clk selection failed\n");  in stm32h7_adc_clk_sel()
120 	return -EINVAL;  in stm32h7_adc_clk_sel()
124 	common->rate = rate / div;  in stm32h7_adc_clk_sel()
127 	clrsetbits_le32(common->base + STM32H7_ADC_CCR,  in stm32h7_adc_clk_sel()
132 	dev_dbg(dev, "Using %s clock/%d source at %ld kHz\n",  in stm32h7_adc_clk_sel()
133 		ckmode ? "bus" : "adc", div, common->rate / 1000);  in stm32h7_adc_clk_sel()
143 	common->base = dev_read_addr_ptr(dev);  in stm32_adc_core_probe()
144 	if (!common->base) {  in stm32_adc_core_probe()
145 		dev_err(dev, "can't get address\n");  in stm32_adc_core_probe()
146 		return -ENOENT;  in stm32_adc_core_probe()
149 	ret = device_get_supply_regulator(dev, "vref-supply", &common->vref);  in stm32_adc_core_probe()
151 		dev_err(dev, "can't get vref-supply: %d\n", ret);  in stm32_adc_core_probe()
155 	ret = regulator_get_value(common->vref);  in stm32_adc_core_probe()
157 		dev_err(dev, "can't get vref-supply value: %d\n", ret);  in stm32_adc_core_probe()
160 	common->vref_uv = ret;  in stm32_adc_core_probe()
162 	ret = clk_get_by_name(dev, "adc", &common->aclk);  in stm32_adc_core_probe()
164 		ret = clk_enable(&common->aclk);  in stm32_adc_core_probe()
166 			dev_err(dev, "Can't enable aclk: %d\n", ret);  in stm32_adc_core_probe()
171 	ret = clk_get_by_name(dev, "bus", &common->bclk);  in stm32_adc_core_probe()
173 		ret = clk_enable(&common->bclk);  in stm32_adc_core_probe()
175 			dev_err(dev, "Can't enable bclk: %d\n", ret);  in stm32_adc_core_probe()
187 	if (clk_valid(&common->bclk))  in stm32_adc_core_probe()
188 		clk_disable(&common->bclk);  in stm32_adc_core_probe()
191 	if (clk_valid(&common->aclk))  in stm32_adc_core_probe()
192 		clk_disable(&common->aclk);  in stm32_adc_core_probe()
198 	{ .compatible = "st,stm32h7-adc-core" },
199 	{ .compatible = "st,stm32mp1-adc-core" },
204 	.name  = "stm32-adc-core",