device-tree-bindings/gpu/nvidia%2Ctegra20-host1x.txt

4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 - interrupts: The interrupt outputs from the controller.
7 - #address-cells: The number of cells used to represent physical base addresses
9 - #size-cells: The number of cells used to represent the size of an address
11 - ranges: The mapping of the host1x address space to the CPU address space.
12 - clocks: Must contain one entry, for the module clock.
13   See ../clocks/clock-bindings.txt for details.
14 - resets: Must contain an entry for each entry in reset-names.
16 - reset-names: Must include the following entries:
17   - host1x
19 The host1x top-level node defines a number of children, each representing one
22 - mpe: video encoder
25   - compatible: "nvidia,tegra<chip>-mpe"
26   - reg: Physical base address and length of the controller's registers.
27   - interrupts: The interrupt outputs from the controller.
28   - clocks: Must contain one entry, for the module clock.
29     See ../clocks/clock-bindings.txt for details.
30   - resets: Must contain an entry for each entry in reset-names.
32   - reset-names: Must include the following entries:
33     - mpe
35 - vi: video input
38   - compatible: "nvidia,tegra<chip>-vi"
39   - reg: Physical base address and length of the controller's registers.
40   - interrupts: The interrupt outputs from the controller.
41   - clocks: Must contain one entry, for the module clock.
42     See ../clocks/clock-bindings.txt for details.
43   - resets: Must contain an entry for each entry in reset-names.
45   - reset-names: Must include the following entries:
46     - vi
48 - epp: encoder pre-processor
51   - compatible: "nvidia,tegra<chip>-epp"
52   - reg: Physical base address and length of the controller's registers.
53   - interrupts: The interrupt outputs from the controller.
54   - clocks: Must contain one entry, for the module clock.
55     See ../clocks/clock-bindings.txt for details.
56   - resets: Must contain an entry for each entry in reset-names.
58   - reset-names: Must include the following entries:
59     - epp
61 - isp: image signal processor
64   - compatible: "nvidia,tegra<chip>-isp"
65   - reg: Physical base address and length of the controller's registers.
66   - interrupts: The interrupt outputs from the controller.
67   - clocks: Must contain one entry, for the module clock.
68     See ../clocks/clock-bindings.txt for details.
69   - resets: Must contain an entry for each entry in reset-names.
71   - reset-names: Must include the following entries:
72     - isp
74 - gr2d: 2D graphics engine
77   - compatible: "nvidia,tegra<chip>-gr2d"
78   - reg: Physical base address and length of the controller's registers.
79   - interrupts: The interrupt outputs from the controller.
80   - clocks: Must contain one entry, for the module clock.
81     See ../clocks/clock-bindings.txt for details.
82   - resets: Must contain an entry for each entry in reset-names.
84   - reset-names: Must include the following entries:
85     - 2d
87 - gr3d: 3D graphics engine
90   - compatible: "nvidia,tegra<chip>-gr3d"
91   - reg: Physical base address and length of the controller's registers.
92   - clocks: Must contain an entry for each entry in clock-names.
93     See ../clocks/clock-bindings.txt for details.
94   - clock-names: Must include the following entries:
96     - 3d
98     - 3d2 (Only required on SoCs with two 3D clocks)
99   - resets: Must contain an entry for each entry in reset-names.
101   - reset-names: Must include the following entries:
102     - 3d
103     - 3d2 (Only required on SoCs with two 3D clocks)
105 - dc: display controller
108   - compatible: "nvidia,tegra<chip>-dc"
109   - reg: Physical base address and length of the controller's registers.
110   - interrupts: The interrupt outputs from the controller.
111   - clocks: Must contain an entry for each entry in clock-names.
112     See ../clocks/clock-bindings.txt for details.
113   - clock-names: Must include the following entries:
114     - dc
116     - parent
117   - resets: Must contain an entry for each entry in reset-names.
119   - reset-names: Must include the following entries:
120     - dc
121   - nvidia,head: The number of the display controller head. This is used to
125   Each display controller node has a child node, named "rgb", that represents
126   the RGB output associated with the controller. It can take the following
128   - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
129   - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
130   - nvidia,edid: supplies a binary EDID blob
131   - nvidia,panel: phandle of a display panel
133 - hdmi: High Definition Multimedia Interface
136   - compatible: "nvidia,tegra<chip>-hdmi"
137   - reg: Physical base address and length of the controller's registers.
138   - interrupts: The interrupt outputs from the controller.
139   - hdmi-supply: supply for the +5V HDMI connector pin
140   - vdd-supply: regulator for supply voltage
141   - pll-supply: regulator for PLL
142   - clocks: Must contain an entry for each entry in clock-names.
143     See ../clocks/clock-bindings.txt for details.
144   - clock-names: Must include the following entries:
145     - hdmi
147     - parent
148   - resets: Must contain an entry for each entry in reset-names.
150   - reset-names: Must include the following entries:
151     - hdmi
154   - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
155   - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
156   - nvidia,edid: supplies a binary EDID blob
157   - nvidia,panel: phandle of a display panel
159 - tvo: TV encoder output
162   - compatible: "nvidia,tegra<chip>-tvo"
163   - reg: Physical base address and length of the controller's registers.
164   - interrupts: The interrupt outputs from the controller.
165   - clocks: Must contain one entry, for the module clock.
166     See ../clocks/clock-bindings.txt for details.
168 - dsi: display serial interface
171   - compatible: "nvidia,tegra<chip>-dsi"
172   - reg: Physical base address and length of the controller's registers.
173   - clocks: Must contain an entry for each entry in clock-names.
174     See ../clocks/clock-bindings.txt for details.
175   - clock-names: Must include the following entries:
176     - dsi
178     - lp
179     - parent
180   - resets: Must contain an entry for each entry in reset-names.
182   - reset-names: Must include the following entries:
183     - dsi
184   - avdd-dsi-supply: phandle of a supply that powers the DSI controller
185   - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying
186     which pads are used by this DSI output and need to be calibrated. See also
187     ../mipi/nvidia,tegra114-mipi.txt.
190   - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
191   - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
192   - nvidia,edid: supplies a binary EDID blob
193   - nvidia,panel: phandle of a display panel
195 - sor: serial output resource
198   - compatible: "nvidia,tegra124-sor"
199   - reg: Physical base address and length of the controller's registers.
200   - interrupts: The interrupt outputs from the controller.
201   - clocks: Must contain an entry for each entry in clock-names.
202     See ../clocks/clock-bindings.txt for details.
203   - clock-names: Must include the following entries:
204     - sor: clock input for the SOR hardware
205     - parent: input for the pixel clock
206     - dp: reference clock for the SOR clock
207     - safe: safe reference for the SOR clock during power up
208   - resets: Must contain an entry for each entry in reset-names.
210   - reset-names: Must include the following entries:
211     - sor
214   - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
215   - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
216   - nvidia,edid: supplies a binary EDID blob
217   - nvidia,panel: phandle of a display panel
220   - nvidia,dpaux: phandle to a DispayPort AUX interface
222 - dpaux: DisplayPort AUX interface
223   - compatible: "nvidia,tegra124-dpaux"
224   - reg: Physical base address and length of the controller's registers.
225   - interrupts: The interrupt outputs from the controller.
226   - clocks: Must contain an entry for each entry in clock-names.
227     See ../clocks/clock-bindings.txt for details.
228   - clock-names: Must include the following entries:
229     - dpaux: clock input for the DPAUX hardware
230     - parent: reference clock
231   - resets: Must contain an entry for each entry in reset-names.
233   - reset-names: Must include the following entries:
234     - dpaux
235   - vdd-supply: phandle of a supply that powers the DisplayPort link
243 		compatible = "nvidia,tegra20-host1x", "simple-bus";
249 		reset-names = "host1x";
251 		#address-cells = <1>;
252 		#size-cells = <1>;
257 			compatible = "nvidia,tegra20-mpe";
262 			reset-names = "mpe";
266 			compatible = "nvidia,tegra20-vi";
271 			reset-names = "vi";
275 			compatible = "nvidia,tegra20-epp";
280 			reset-names = "epp";
284 			compatible = "nvidia,tegra20-isp";
289 			reset-names = "isp";
293 			compatible = "nvidia,tegra20-gr2d";
298 			reset-names = "2d";
302 			compatible = "nvidia,tegra20-gr3d";
306 			reset-names = "3d";
310 			compatible = "nvidia,tegra20-dc";
315 			clock-names = "dc", "parent";
317 			reset-names = "dc";
325 			compatible = "nvidia,tegra20-dc";
330 			clock-names = "dc", "parent";
332 			reset-names = "dc";
340 			compatible = "nvidia,tegra20-hdmi";
345 			clock-names = "hdmi", "parent";
347 			reset-names = "hdmi";
352 			compatible = "nvidia,tegra20-tvo";
359 		dsi {
360 			compatible = "nvidia,tegra20-dsi";
364 			clock-names = "dsi", "parent";
366 			reset-names = "dsi";