Lines Matching full:controller

3 Tegra186 contains two GPIO controllers; a main controller and an "AON"
4 controller. This binding document applies to both controllers. The register
9 The Tegra186 GPIO controller allows software to set the IO direction of, and
11 package balls is under the control of a separate pin controller HW block. Two
36 The number of ports implemented by each GPIO controller varies. The number of
37 implemented GPIOs within each port varies. GPIO registers within a controller
40 The mapping from port name to the GPIO controller that implements that port, and
41 the mapping from port name to register offset within a controller, are both
45 sorted within a particular controller. Drivers need to map between the DT GPIO
48 Each GPIO controller can generate a number of interrupt signals. Each signal
50 number of interrupt signals generated by a controller varies as a rough function
52 both the overall controller HW module and the sets-of-ports as "controllers".
54 Each GPIO controller in fact generates multiple interrupts signals for each set
77         b) All physical aliases that exist in the controller. This is
94 - gpio-controller
96     Marks the device node as a GPIO controller/provider.
108 - interrupt-controller
110     Marks the device node as an interrupt controller/provider.
128 #include <dt-bindings/interrupt-controller/irq.h>
143 	gpio-controller;
145 	interrupt-controller;
157 	gpio-controller;
159 	interrupt-controller;