device-tree-bindings/gpio/intel%2Cx86-broadwell-pinctrl.txt

3 Pin-muxing on broadwell devices can be described with a node for the PINCTRL
9 - compatible : "intel,x86-broadwell-pinctrl"
11 Pin state nodes must be sub-nodes of the pinctrl master node. The must have
13 - mode-gpio	- forces the pin into GPIO mode
14 - output-value	- sets the default output value of the GPIO, 0 (low, default)
16 - direction	- sets the direction of the gpio, either PIN_INPUT (default)
18 - invert	- the input pin is inverted
19 - trigger	- sets the trigger type, either TRIGGER_EDGE (default) or
21 - sense-disable - the input state sense is disabled
22 - owner		0 sets the owner of the pin, either OWNER_ACPI (default) or
24 - route		- sets whether the pin is routed, either PIRQ_APIC_MASK or
26 - irq-enable	- the interrupt is enabled
27 - reset-rsmrst	- the pin will only be reset by RSMRST
28 - pirq-apic	- the pin will be routed to the IOxAPIC
33 The pin configuration node is also a sub-node of the pinctrl master node, but
36 - config	- configuration to use for each pin. Each entry has of 3 cells:
37 			- GPIO number (0..94)
38 			- phandle of configuration (above)
39 			- interrupt number (0..15)
47 	compatible = "intel,x86-broadwell-pinctrl";
50 	gpio_unused: gpio-unused {
51 		mode-gpio;
54 		sense-disable;
57 	gpio_acpi_sci: acpi-sci {
58 		mode-gpio;
64 	gpio_acpi_smi: acpi-smi {
65 		mode-gpio;
71 	gpio_input: gpio-input {
72 		mode-gpio;
77 	gpio_input_invert: gpio-input-invert {
78 		mode-gpio;
84 	gpio_native: gpio-native {
87 	gpio_out_high: gpio-out-high {
88 		mode-gpio;
90 		output-value = <1>;
92 		sense-disable;
95 	gpio_out_low: gpio-out-low {
96 		mode-gpio;
98 		output-value = <0>;
100 		sense-disable;
103 	gpio_pirq: gpio-pirq {
104 		mode-gpio;
107 		pirq-apic = <PIRQ_APIC_ROUTE>;
157 			<45 &gpio_acpi_sci 0>,	/* dsp_int - codec wake */
158 			<46 &gpio_pirq 6>,	/* hotword_det_l_3v3 (pirqo) - codec irq */