device-tree-bindings/firmware/nvidia%2Ctegra186-bpmp.txt

11 - name : Should be bpmp
12 - compatible
15     - "nvidia,tegra186-bpmp"
16 - mboxes : The phandle of mailbox controller and the mailbox specifier.
17 - shmem : List of the phandle of the TX and RX shared memory area that
19 - #clock-cells : Should be 1.
20 - #power-domain-cells : Should be 1.
21 - #reset-cells : Should be 1.
27 - .../mailbox/mailbox.txt
28 - .../mailbox/nvidia,tegra186-hsp.txt
34 - .../clock/clock-bindings.txt
35 - <dt-bindings/clock/tegra186-clock.h>
36 - ../power/power_domain.txt
37 - <dt-bindings/power/tegra186-powergate.h>
38 - .../reset/reset.txt
39 - <dt-bindings/reset/tegra186-reset.h>
43 bindings represent each I2C controller as a device tree node. Such nodes should
46 Software can determine whether a child node of the BPMP node represents a device
48 represents a device that can be instantiated. Nodes without a compatible
53 The BPMP firmware defines no single global name-/numbering-space for such
56 hypothetical SPI bus service). As such, child device nodes will have no reg
57 property, and the BPMP node will have no #address-cells or #size-cells property.
60 -----------------------------------
63 predefined and work on top of sysram, which is an SRAM inside the chip.
65 See ".../sram/sram.txt" for the bindings.
71 	#mbox-cells = <2>;
75 	compatible = "nvidia,tegra186-sysram", "mmio-sram";
77 	#address-cells = <2>;
78 	#size-cells = <2>;
82 		compatible = "nvidia,tegra186-bpmp-shmem";
87 		compatible = "nvidia,tegra186-bpmp-shmem";
93 	compatible = "nvidia,tegra186-bpmp";
96 	#clock-cells = <1>;
97 	#power-domain-cells = <1>;
98 	#reset-cells = <1>;