device-tree-bindings/firmware/nvidia%2Ctegra186-bpmp.txt

1 NVIDIA Tegra Boot and Power Management Processor (BPMP)
3 The BPMP is a specific processor in Tegra chip, which is designed for
5 management, and reset control tasks from the CPU. The binding document
6 defines the resources that would be used by the BPMP firmware driver,
7 which can create the interprocessor communication (IPC) between the CPU
8 and BPMP.
11 - name : Should be bpmp
12 - compatible
15     - "nvidia,tegra186-bpmp"
16 - mboxes : The phandle of mailbox controller and the mailbox specifier.
17 - shmem : List of the phandle of the TX and RX shared memory area that
18 	  the IPC between CPU and BPMP is based on.
19 - #clock-cells : Should be 1.
20 - #power-domain-cells : Should be 1.
21 - #reset-cells : Should be 1.
27 - .../mailbox/mailbox.txt
28 - .../mailbox/nvidia,tegra186-hsp.txt
34 - .../clock/clock-bindings.txt
35 - <dt-bindings/clock/tegra186-clock.h>
36 - ../power/power_domain.txt
37 - <dt-bindings/power/tegra186-powergate.h>
38 - .../reset/reset.txt
39 - <dt-bindings/reset/tegra186-reset.h>
41 The BPMP implements some services which must be represented by separate nodes.
44 be nested directly inside the main BPMP node.
46 Software can determine whether a child node of the BPMP node represents a device
49 property may be used to provide configuration information regarding the BPMP
53 The BPMP firmware defines no single global name-/numbering-space for such
55 the numbering scheme for any other service the BPMP may provide (e.g. a future
57 property, and the BPMP node will have no #address-cells or #size-cells property.
59 The shared memory bindings for BPMP
60 -----------------------------------
62 The shared memory area for the IPC TX and RX between CPU and BPMP are
71 	#mbox-cells = <2>;
75 	compatible = "nvidia,tegra186-sysram", "mmio-sram";
77 	#address-cells = <2>;
78 	#size-cells = <2>;
82 		compatible = "nvidia,tegra186-bpmp-shmem";
87 		compatible = "nvidia,tegra186-bpmp-shmem";
92 bpmp {
93 	compatible = "nvidia,tegra186-bpmp";
96 	#clock-cells = <1>;
97 	#power-domain-cells = <1>;
98 	#reset-cells = <1>;