device-tree-bindings/adc/st%2Cstm32-adc.txt

3 STM32 ADC is a successive approximation analog-to-digital converter.
5 in single, continuous, scan or discontinuous mode. Result of the ADC is
6 stored in a left-aligned or right-aligned 32-bit data register.
10 voltage goes beyond the user-defined, higher or lower thresholds.
16 - regular conversion can be done in sequence, running in background
17 - injected conversions have higher priority, and so have the ability to
22 -----------------------------------
24 - compatible: Should be one of:
25   "st,stm32f4-adc-core"
26   "st,stm32h7-adc-core"
27   "st,stm32mp1-adc-core"
28 - reg: Offset and length of the ADC block register set.
29 - interrupts: One or more interrupts for ADC block. Some parts like stm32f4
32 - clocks: Core can use up to two clocks, depending on part used:
33   - "adc" clock: for the analog circuitry, common to all ADCs.
36   - "bus" clock: for registers access, common to all ADCs.
39 - clock-names: Must be "adc" and/or "bus" depending on part used.
40 - interrupt-controller: Identifies the controller node as interrupt-parent
41 - vref-supply: Phandle to the vref input analog reference voltage.
42 - #interrupt-cells = <1>;
43 - #address-cells = <1>;
44 - #size-cells = <0>;
47 - A pinctrl state named "default" for each ADC channel may be defined to set
51 -----------------------------------
56 - compatible: Should be one of:
57   "st,stm32f4-adc"
58   "st,stm32h7-adc"
59   "st,stm32mp1-adc"
60 - reg: Offset of ADC instance in ADC block (e.g. may be 0x0, 0x100, 0x200).
61 - clocks: Input clock private to this ADC instance. It's required only on
63 - interrupt-parent: Phandle to the parent interrupt controller.
64 - interrupts: IRQ Line for the ADC (e.g. may be 0 for adc@0, 1 for adc@100 or
66 - st,adc-channels: List of single-ended channels muxed for this ADC.
69 - st,adc-diff-channels: List of differential channels muxed for this ADC.
71   instead of single-ended (e.g. stm32h7). List here positive and negative
74   Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is required.
76   single-ended and some other ones as differential (mixed). But channels
77   can't be configured both as single-ended and differential (invalid).
78 - #io-channel-cells = <1>: See the IIO bindings section "IIO consumers" in
79   Documentation/devicetree/bindings/iio/iio-bindings.txt
82 - dmas: Phandle to dma channel for this ADC instance.
84 - dma-names: Must be "rx" when dmas property is being used.
85 - assigned-resolution-bits: Resolution (bits) to use for conversions. Must
90 - st,min-sample-time-nsecs: Minimum sampling time in nanoseconds.
93   This can be either one value or an array that matches 'st,adc-channels' list,
98 		compatible = "st,stm32f4-adc-core";
102 		clock-names = "adc";
103 		vref-supply = <&reg_vref>;
104 		interrupt-controller;
105 		pinctrl-names = "default";
106 		pinctrl-0 = <&adc3_in8_pin>;
108 		#interrupt-cells = <1>;
109 		#address-cells = <1>;
110 		#size-cells = <0>;
113 			compatible = "st,stm32f4-adc";
114 			#io-channel-cells = <1>;
117 			interrupt-parent = <&adc>;
119 			st,adc-channels = <8>;
121 			dma-names = "rx";
122 			assigned-resolution-bits = <8>;
129 - channel 1 as single-ended
130 - channels 2 & 3 as differential (with resp. 6 & 7 negative inputs)
133 		compatible = "st,stm32h7-adc-core";
136 			compatible = "st,stm32h7-adc";
138 			st,adc-channels = <1>;
139 			st,adc-diff-channels = <2 6>, <3 7>;