Lines Matching full:slave

15 	a) Master and slave can be SOCs in one board or SOCs in separate boards.
18 	c) Only Master has NorFlash for booting, and all the Master's and Slave's
20 	d) Slave has its own EEPROM for RCW and PBI.
21 	e) Slave's RCW should configure the SerDes for SRIO or PCIE boot port, set
27 	| NorFlash|<----->| Master  |SRIO or PCIE |  Slave  |<---->[EEPROM]
37 	1. Slave's RCW example for boot from SRIO port 1 and all cores in holdoff.
44 	2. Slave's RCW example for boot from PCIE port 1 and all cores in holdoff.
52 		a) Update RCW for slave with boot from SRIO or PCIE port 1 configuration.
53 		b) Program slave's U-Boot image, UCode, and ENV parameters into master's
62 		   Then, it will finish necessary configurations for slave's boot from
64 		e) Master will set inbound SRIO or PCIE windows covered slave's U-Boot
66 		f) Master will set an inbound SRIO or PCIE window covered slave's UCode
69 		   slave's registers for the core's releasing.
70 		h) Since all cores of slave in holdoff, slave should be powered on before
72 		   startup phase of the slave from SRIO or PCIE, it will finish some
74 		i) Slave will set a specific TLB entry for the boot process.
75 		j) Slave will set a LAW entry with the TargetID SRIO or PCIE port 1 for
77 		k) Slave will set a specific TLB entry in order to fetch UCode and ENV
79 		l) Slave will set a LAW entry with the TargetID SRIO or PCIE port 1 for
85 	1. Slave's RCW with SRIO or PCIE boot configurations, and all cores in holdoff
96 	   For slave, U-Boot image should be generated specifically by
100 	   For example, slave U-Boot image used on P4080DS should be compiled with
105 	   For a specific environment, the addresses of the slave's U-Boot image,
114 NOTE: When the Slave's ENV parameters are stored in Master's NorFlash,
117       the Slave's u-boot environment, because the Slave can not erase,