Lines Matching +full:load +full:- +full:reduced
2 --------
6 -------------
7 The B4860 QorIQ Qonverge device is a Freescale high-end, multicore SoC based on
11 expanding wireless markets, such as 3GLTE (FDD and TDD), LTE-Advanced, and UMTS.
13 The B4860 is a highly-integrated StarCore and Power Architecture processor that
15 . Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
16 clusters-each core runs up to 1.2 GHz, with an architecture highly optimized for
18 . Four dual-thread e6500 Power Architecture processors organized in one cluster-each
20 . Two DDR3/3L controllers for high-speed, industry-standard memory interface each
22 . MAPLE-B3 hardware acceleration-for forward error correction schemes including
30 non-coherent out of order transactions with prioritization and bandwidth
33 . Frame Manager (FMan), which supports in-line packet parsing and general
34 classification to enable policing and QoS-based packet distribution
36 of queue management, task management, load distribution, flow ordering, buffer
38 . Security engine (SEC 5.3)-crypto-acceleration for protocols such as IPsec,
40 . RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
43 bandwidth saving and high utilization of processor elements. The 9856-Kbyte
50 . Sixteen 10-GHz SerDes lanes serving:
52 - Each supports up to 4 lanes and a total of up to 8 lanes
53 . Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-less
55 . Two 10-Gbit Ethernet controllers (10GEC)
56 . Six 1G/2.5-Gbit Ethernet controllers for network communications
61 . 182 32-bit timers
64 ------------------
65 - DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 4 GB
67 - DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 2 GB
69 - SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point 16x16 switch
71 - SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point 8x8 switch VSC3308
72 - USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
73 B4860 UART port is available over USB-to-UART translator USB2SER or over RS232 flat cable.
74 - A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45 copper connectors
75 for Stand-alone mode and to the 1000Base-X over AMC MicroTCA connector ports 0 and 2 for
77 - The B4860 configuration may be loaded from nine bits coded reset configuration reset source. The
78 RCW source is set by appropriate DIP-switches:
79 - 16-bit NOR Flash / PROMJet
80 - QIXIS 8-bit NOR Flash Emulator
81 - 8-bit NAND Flash
82 - 24-bit SPI Flash
83 - Long address I2C EEPROM
84 - Available debug interfaces are:
85 - On-board eCWTAP controller with ETH and USB I/F
86 - JTAG/COP 16-pin header for any external TAP controller
87 - External JTAG source over AMC to support B2B configuration
88 - 70-pin Aurora debug connector
89 - QIXIS (FPGA) logic:
90 - 2 KB internal memory space including
91 - IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK, DDRCLK1,2 and
93 - Two 8T49N222A SerDes ref clock devices support two SerDes port clock frequency - total four
97 --------------------
100 --------------------
101 B4420 is a reduced personality of B4860 with less core/clusters(both SC3900 and e6500), less DDR
102 controllers, less serdes lanes, less SGMII interfaces and reduced target frequencies.
105 ----------------------------------------
117 -------------------------
120 ----------------
130 SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
143 -------------------------
146 ----------------
155 SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
168 ----------------------
173 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB
190 0xC_3000_0000 0xC_3FFF_FFFF sRIO-2 I/O 256 MB
191 0xC_2000_0000 0xC_2FFF_FFFF sRIO-1 I/O 256 MB
198 ----------------------
203 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB
220 0xC_3000_0000 0xC_3FFF_FFFF sRIO-2 I/O 256 MB
221 0xC_2000_0000 0xC_2FFF_FFFF sRIO-1 I/O 256 MB
228 ------------------------------------------
230 0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
231 0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
237 0xEDF40000 0xEDFFFFFF U-Boot (alternate bank) 768KB
238 0xEDF20000 0xEDF3FFFF U-Boot env (alternate bank) 128KB
246 --------------------------------------------------------------
249 1. U-Boot environment variable hwconfig
270 2)Flash vbank2 with b4420 rcw and U-Boot
282 5. Switching between NOR and NAND boot(RCW src changed from NOR <-> NAND)
312 Under U-Boot these network interfaces are recognized as:
316 . eth2 -> fm1-gb2
317 . eth3 -> fm1-gb3
318 . eth4 -> fm1-gb4
319 . eth5 -> fm1-gb5
325 Under U-Boot these network interfaces are recognized as:
329 . eth2 -> fm1-gb2
330 . eth3 -> fm1-gb3
333 ----------------------------------
336 U-Boot(768 KB) from flash to DDR.
337 Finally SPL transer control to U-Boot for futher booting.
340 - Executes within 256K
341 - No relocation required
343 Run time view of SPL framework during boot :-
344 -----------------------------------------------
346 -----------------------------------------------
349 -----------------------------------------------
351 -----------------------------------------------
353 -----------------------------------------------
355 -----------------------------------------------
357 -----------------------------------------------
358 U-Boot SPL | 0xFFFD8000 (160KB) |
359 -----------------------------------------------
362 ------------------------------------------
364 0x000000 0x0FFFFF U-Boot 1MB
365 0x140000 0x15FFFF U-Boot env 128KB