Lines Matching +full:no +full:- +full:loopback +full:- +full:test
1 Power-On-Self-Test support in U-Boot
2 ------------------------------------
4 This project is to support Power-On-Self-Test (POST) in U-Boot.
6 1. High-level requirements
11 and running Power-On-Self-Test in U-Boot. This framework shall
21 The framework shall allow run-time configuration of the lists
22 of tests running on normal/power-fail booting.
31 3) The following POST tests shall be developed for MPC823E-based
34 o) CPU test
35 o) Cache test
36 o) Memory test
37 o) Ethernet test
38 o) Serial channels test
39 o) Watchdog timer test
40 o) RTC test
41 o) I2C test
42 o) SPI test
43 o) USB test
51 enhancing U-Boot/Linux to provide a common framework for running POST
54 2.1. Hardware-independent POST layer
56 A new optional module will be added to U-Boot, which will run POST
57 tests and collect their results at boot time. Also, U-Boot will
61 The list of available POST tests will be configured at U-Boot build
65 1) Tests running on power-on booting only
68 power-on reset (e.g. watchdog test)
73 time and can be run on the regular basis (e.g. CPU test)
75 3) Tests running in special "slow test mode" only
78 and cannot be run regularly (e.g. strong memory test, I2C test)
85 For example, SDRAM test may run in both normal and "slow test" mode.
86 In normal mode, SDRAM test may perform a fast superficial memory test
87 only, while running in slow test mode it may perform a full memory
88 check-up.
106 may cause system rebooting (e.g. watchdog test). For such tests, the
107 layer will automatically detect rebooting and will notify the test
113 rest of U-Boot.
117 #define POST_POWERON 0x01 /* test runs on power-on booting */
118 #define POST_NORMAL 0x02 /* test runs on normal booting */
119 #define POST_SLOWTEST 0x04 /* test is slow, enabled by key press */
120 #define POST_POWERTEST 0x08 /* test runs after watchdog reset */
121 #define POST_ROM 0x100 /* test runs in ROM */
122 #define POST_RAM 0x200 /* test runs in RAM */
123 #define POST_MANUAL 0x400 /* test can be executed manually */
124 #define POST_REBOOT 0x800 /* test may cause rebooting */
125 #define POST_PREREL 0x1000 /* test runs before relocation */
131 This routine will run the test (or the group of tests) specified
133 argument is not NULL, the test with this name will be performed,
138 mode the test is executed in (power-on, normal, power-fail,
144 relocate the POST test table.
150 particular test if name is not NULL.
159 Also, the following board-specific routines will be called from the
160 U-Boot common code:
166 power-on long-running tests shall be executed or not ("normal"
167 versus "slow" test mode).
170 filled at U-Boot build time. The format of entry in this array will
178 int (*test)(bd_t *bd, int flags);
183 This field will contain a short name of the test, which will be
184 used in logs and on listing POST tests (e.g. CPU test).
188 This field will keep a name for identifying the test on manual
194 This field will contain a detailed description of the test,
201 above, which will specify the mode the test is running in
202 (power-on, normal, power-fail or manual mode), the moment it
206 o) test
209 perform the test, which will take 2 arguments. The first
212 mode the test is running in (POST_POWERON, POST_NORMAL,
214 the test caused system rebooting (POST_REBOOT). The routine will
215 return 0 on successful execution of the test, and 1 if the test
218 The lists of the POST tests that should be run at power-on/normal/
219 power-fail booting will be kept in the environment. Namely, the
223 2.1.2. Test results
229 --------------------------------------------
231 <test-specific output>
233 --------------------------------------------
238 save it in non-volatile RAM (NVRAM), transfer it to a dedicated
243 All POST-related code will be #ifdef'ed with the CONFIG_POST macro.
251 "On-board peripherals test", "board", \
252 " This test performs full check-up of the " \
253 "on-board hardware.", \
265 "Cache test", "cache", \
266 " This test verifies the CPU cache operation.", \
271 A new subdirectory will be created in the U-Boot root directory. It
273 tests. Each POST test in this directory will be placed into a
277 way will be used only if the test subtantially uses the driver.
282 user-space library will be developed to provide the POST interface
287 A new command, diag, will be added to U-Boot. This command will be
296 cache - cache test
297 cpu - CPU test
298 enet - SCC/FCC ethernet test
307 cpu - CPU test
308 This test verifies the arithmetic logic unit of CPU.
309 cache - cache test
310 This test verifies the CPU cache operation.
314 executed. If no tests are specified, all available tests will be
327 handler of the power-fail IRQ on booting. Being called, the handler
333 The POST layer of U-Boot will check whether the system runs in
334 power-fail mode. If it does, the system will be powered off after
341 test, this means successful operation of the timer.
347 the POST layer will store an identification number of the test in a
350 failed one. On second execution of the failed test, the POST_REBOOT
351 bit flag will be set in the flag argument to the test routine. This
353 example, the watchdog timer test may have the following
359 "Watchdog timer test", "watchdog", \
360 " This test checks the watchdog timer.", \
372 /* Test passed */
377 /* 10-second delay */
386 2.2. Hardware-specific details
388 This project will also develop a set of POST tests for MPC8xx- based
396 o) CPU test
398 This test will check the arithmetic logic unit (ALU) of CPU. The
399 test will take several milliseconds and will run on normal
402 o) Cache test
404 This test will verify the CPU cache (L1 cache). The test will
407 o) Memory test
409 This test will examine RAM and check it for errors. The test
411 amount of RAM will be checked. On power-fail booting a fool
412 memory check-up will be performed.
414 2.2.1.1. CPU test
416 This test will verify the following ALU instructions:
425 a general-purpose register (mfcr) and comparing this value with
429 general-purpose register (mfcr) and comparing the value of this
433 4-bit condition fields, moving the value of the conditional
434 register to a general-purpose register (mfcr) and comparing it
441 To verify these instructions the test will run them with
444 the test will contain a pre-built table containing the
445 description of each test case: the instruction, the values of
455 The test will contain a pre-built table of instructions,
457 register. For each table entry, the test will cyclically use
463 general-purpose registers.
470 The test scheme will be identical to that from the previous
478 The test scheme will be identical to that from the previous
491 such combinations will be pre-built and linked in U-Boot at
499 All operations will be performed on a 16-byte array. The array
500 will be 4-byte aligned. The base register will point to offset
501 8. The immediate offset (index register) will range in [-8 ...
502 +7]. The test cases will be composed so that they will not cause
503 alignment exceptions. The test will contain a pre-built table
504 describing all test cases. For store instructions, the table
507 executing the instruction, the test will verify the contents of
513 the test will verify the value of the destination register and
520 The CPU test will run in RAM in order to allow run-time modification
523 2.2.1.2 Special-Purpose Registers Tests
527 2.2.1.3. Cache test
529 To verify the data cache operation the following test scenarios will
532 1) Basic test #1
534 - turn on the data cache
535 - switch the data cache to write-back or write-through mode
536 - invalidate the data cache
537 - write the negative pattern to a cached area
538 - read the area
542 2) Basic test #2
544 - turn on the data cache
545 - switch the data cache to write-back or write-through mode
546 - invalidate the data cache
547 - write the zero pattern to a cached area
548 - turn off the data cache
549 - write the negative pattern to the area
550 - turn on the data cache
551 - read the area
555 3) Write-through mode test
557 - turn on the data cache
558 - switch the data cache to write-through mode
559 - invalidate the data cache
560 - write the zero pattern to a cached area
561 - flush the data cache
562 - write the negative pattern to the area
563 - turn off the data cache
564 - read the area
568 4) Write-back mode test
570 - turn on the data cache
571 - switch the data cache to write-back mode
572 - invalidate the data cache
573 - write the negative pattern to a cached area
574 - flush the data cache
575 - write the zero pattern to the area
576 - invalidate the data cache
577 - read the area
581 To verify the instruction cache operation the following test
584 1) Basic test #1
586 - turn on the instruction cache
587 - unlock the entire instruction cache
588 - invalidate the instruction cache
589 - lock a branch instruction in the instruction cache
590 - replace the branch instruction with "nop"
591 - jump to the branch instruction
592 - check that the branch instruction was executed
594 2) Basic test #2
596 - turn on the instruction cache
597 - unlock the entire instruction cache
598 - invalidate the instruction cache
599 - jump to a branch instruction
600 - check that the branch instruction was executed
601 - replace the branch instruction with "nop"
602 - invalidate the instruction cache
603 - jump to the branch instruction
604 - check that the "nop" instruction was executed
606 The CPU test will run in RAM in order to allow run-time modification
609 2.2.1.4. Memory test
611 The memory test will verify RAM using sequential writes and reads
612 to/from RAM. Specifically, there will be several test cases that will
613 use different patterns to verify RAM. Each test case will first fill
621 4) bit-flip pattern ((1 << (offset % 32)), ~(1 << (offset % 32)))
627 to detect far-located errors, i.e. situations when writing to one
632 Being run in normal mode, the test will verify only small 4Kb regions
634 following areas will be verified: 0x00000000-0x00000800,
635 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800-
636 0x04000000. If the test is run in power-fail mode, it will verify the
639 The memory test will run in ROM before relocating U-Boot to RAM in
645 peculiarities and use common U-Boot interfaces only. These tests do
648 2.2.2.1. I2C test
652 CONFIG_SYS_POST_I2C_ADDRS the I2C test will pass if all devices
653 listed in CONFIG_SYS_POST_I2C_ADDRS are found, and no additional
655 the test will pass if any I2C device is found.
659 CONFIG_SYS_POST_I2C_ADDRS. The I2C POST test will pass regardless
665 2.2.2.2. Watchdog timer test
667 To test the watchdog timer the scheme mentioned above (refer to
668 section "Hazardous tests") will be used. Namely, this test will be
670 test routine will make a 10-second delay. If the system does not
672 the test fails. If the system reboots, on the second iteration the
673 POST_REBOOT bit will be set in the flag argument to the test routine.
674 The test routine will check this bit and report a success if it is
677 2.2.2.3. RTC test
679 The RTC test will use the rtc_get()/rtc_set() routines. The following
685 period of time (5-10 seconds).
690 boundary and reading it after its passing the boundary. The test
691 will be performed for both leap- and nonleap-years.
705 The internal (local) loopback mode will be used to test SCC. To do
708 use external loopback for testing. That will need appropriate
711 The test routines for the SCC ethernet tests will be located in
716 To perform these tests the internal (local) loopback mode will be
720 "external" loopback test using a loopback cable. In this case, the
721 test will be executed manually.
723 The test routine for the SMC/SCC UART tests will be located in
726 2.2.3.3. USB test
730 2.2.3.4. SPI test