Lines Matching +full:allow +full:- +full:set +full:- +full:time
1 Power-On-Self-Test support in U-Boot
2 ------------------------------------
4 This project is to support Power-On-Self-Test (POST) in U-Boot.
6 1. High-level requirements
11 and running Power-On-Self-Test in U-Boot. This framework shall
16 The framework shall allow adding/removing/replacing POST tests.
21 The framework shall allow run-time configuration of the lists
22 of tests running on normal/power-fail booting.
31 3) The following POST tests shall be developed for MPC823E-based
51 enhancing U-Boot/Linux to provide a common framework for running POST
54 2.1. Hardware-independent POST layer
56 A new optional module will be added to U-Boot, which will run POST
57 tests and collect their results at boot time. Also, U-Boot will
58 support running POST tests manually at any time by executing a
61 The list of available POST tests will be configured at U-Boot build
62 time. The POST layer will allow the developer to add any custom POST
65 1) Tests running on power-on booting only
68 power-on reset (e.g. watchdog test)
73 time and can be run on the regular basis (e.g. CPU test)
77 This group will contain POST tests that consume much time
88 check-up.
113 rest of U-Boot.
117 #define POST_POWERON 0x01 /* test runs on power-on booting */
136 twice with name set to NULL, once from board_init_f() and once
138 mode the test is executed in (power-on, normal, power-fail,
159 Also, the following board-specific routines will be called from the
160 U-Boot common code:
166 power-on long-running tests shall be executed or not ("normal"
170 filled at U-Boot build time. The format of entry in this array will
202 (power-on, normal, power-fail or manual mode), the moment it
218 The lists of the POST tests that should be run at power-on/normal/
219 power-fail booting will be kept in the environment. Namely, the
229 --------------------------------------------
231 <test-specific output>
233 --------------------------------------------
238 save it in non-volatile RAM (NVRAM), transfer it to a dedicated
243 All POST-related code will be #ifdef'ed with the CONFIG_POST macro.
251 "On-board peripherals test", "board", \
252 " This test performs full check-up of the " \
253 "on-board hardware.", \
259 file will contain common POST declarations and will define a set of
271 A new subdirectory will be created in the U-Boot root directory. It
281 The POST framework will allow to develop and run standalone tests. A
282 user-space library will be developed to provide the POST interface
287 A new command, diag, will be added to U-Boot. This command will be
296 cache - cache test
297 cpu - CPU test
298 enet - SCC/FCC ethernet test
307 cpu - CPU test
309 cache - cache test
327 handler of the power-fail IRQ on booting. Being called, the handler
333 The POST layer of U-Boot will check whether the system runs in
334 power-fail mode. If it does, the system will be powered off after
345 the POST_REBOOT bit flag set in the flag field of the correspondent
349 this variable and if it is set will skip over the tests preceding the
351 bit flag will be set in the flag argument to the test routine. This
352 will allow to detect system rebooting on the previous iteration. For
377 /* 10-second delay */
386 2.2. Hardware-specific details
388 This project will also develop a set of POST tests for MPC8xx- based
411 amount of RAM will be checked. On power-fail booting a fool
412 memory check-up will be performed.
425 a general-purpose register (mfcr) and comparing this value with
429 general-purpose register (mfcr) and comparing the value of this
433 4-bit condition fields, moving the value of the conditional
434 register to a general-purpose register (mfcr) and comparing it
444 the test will contain a pre-built table containing the
455 The test will contain a pre-built table of instructions,
463 general-purpose registers.
491 such combinations will be pre-built and linked in U-Boot at
492 build time.
499 All operations will be performed on a 16-byte array. The array
500 will be 4-byte aligned. The base register will point to offset
501 8. The immediate offset (index register) will range in [-8 ...
503 alignment exceptions. The test will contain a pre-built table
520 The CPU test will run in RAM in order to allow run-time modification
523 2.2.1.2 Special-Purpose Registers Tests
534 - turn on the data cache
535 - switch the data cache to write-back or write-through mode
536 - invalidate the data cache
537 - write the negative pattern to a cached area
538 - read the area
544 - turn on the data cache
545 - switch the data cache to write-back or write-through mode
546 - invalidate the data cache
547 - write the zero pattern to a cached area
548 - turn off the data cache
549 - write the negative pattern to the area
550 - turn on the data cache
551 - read the area
555 3) Write-through mode test
557 - turn on the data cache
558 - switch the data cache to write-through mode
559 - invalidate the data cache
560 - write the zero pattern to a cached area
561 - flush the data cache
562 - write the negative pattern to the area
563 - turn off the data cache
564 - read the area
568 4) Write-back mode test
570 - turn on the data cache
571 - switch the data cache to write-back mode
572 - invalidate the data cache
573 - write the negative pattern to a cached area
574 - flush the data cache
575 - write the zero pattern to the area
576 - invalidate the data cache
577 - read the area
586 - turn on the instruction cache
587 - unlock the entire instruction cache
588 - invalidate the instruction cache
589 - lock a branch instruction in the instruction cache
590 - replace the branch instruction with "nop"
591 - jump to the branch instruction
592 - check that the branch instruction was executed
596 - turn on the instruction cache
597 - unlock the entire instruction cache
598 - invalidate the instruction cache
599 - jump to a branch instruction
600 - check that the branch instruction was executed
601 - replace the branch instruction with "nop"
602 - invalidate the instruction cache
603 - jump to the branch instruction
604 - check that the "nop" instruction was executed
606 The CPU test will run in RAM in order to allow run-time modification
621 4) bit-flip pattern ((1 << (offset % 32)), ~(1 << (offset % 32)))
627 to detect far-located errors, i.e. situations when writing to one
634 following areas will be verified: 0x00000000-0x00000800,
635 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800-
636 0x04000000. If the test is run in power-fail mode, it will verify the
639 The memory test will run in ROM before relocating U-Boot to RAM in
640 order to allow RAM modification without saving its contents.
645 peculiarities and use common U-Boot interfaces only. These tests do
670 test routine will make a 10-second delay. If the system does not
673 POST_REBOOT bit will be set in the flag argument to the test routine.
675 set.
682 o) Time uniformity
685 period of time (5-10 seconds).
691 will be performed for both leap- and nonleap-years.
695 This project will develop a set of tests verifying the peripheral