Lines Matching +full:system +full:- +full:ctl
1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2009 Reinhard Arlt, reinhard.arlt@esd-electronics.com
7 * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com
44 if (busdevfn == -1) { in tsi148_init()
46 return -1; in tsi148_init()
55 return -1; in tsi148_init()
59 dev->busdevfn = busdevfn; in tsi148_init()
63 dev->uregs = (TSI148 *)val; in tsi148_init()
65 debug("Tsi148: Base : %p\n", dev->uregs); in tsi148_init()
69 readl(&dev->uregs->pci_id)); in tsi148_init()
70 if (((LPCI_DEVICE << 16) | LPCI_VENDOR) != readl(&dev->uregs->pci_id)) { in tsi148_init()
71 printf("Tsi148: Cannot read PCI-ID via Mapping: %08x\n", in tsi148_init()
72 readl(&dev->uregs->pci_id)); in tsi148_init()
73 result = -1; in tsi148_init()
77 debug("Tsi148: PCI_BS = %08X\n", readl(&dev->uregs->pci_mbarl)); in tsi148_init()
79 dev->pci_bs = readl(&dev->uregs->pci_mbarl); in tsi148_init()
83 __raw_writel(htonl(0x00000000), &dev->uregs->outbound[j].otat); in tsi148_init()
84 __raw_writel(htonl(0x00000000), &dev->uregs->inbound[j].itat); in tsi148_init()
88 __raw_writel(htonl(0x00000084), &dev->uregs->vctrl); in tsi148_init()
91 if ((__raw_readl(&dev->uregs->vstat) & 0x00000100) != 0) in tsi148_init()
92 printf("Tsi148: System Controller!\n"); in tsi148_init()
94 printf("Tsi148: Not System Controller!\n"); in tsi148_init()
101 __raw_writel(htonl(0x00000000), &dev->uregs->inten); in tsi148_init()
103 __raw_writel(htonl(0x00000000), &dev->uregs->inteo); in tsi148_init()
106 __raw_writel(htonl(0x03ff3f00), &dev->uregs->intc); in tsi148_init()
108 __raw_writel(htonl(0x00000000), &dev->uregs->intm1); in tsi148_init()
109 __raw_writel(htonl(0x00000000), &dev->uregs->intm2); in tsi148_init()
112 val = __raw_readl(&dev->uregs->vstat); in tsi148_init()
114 __raw_writel(val, &dev->uregs->vstat); in tsi148_init()
129 * Create pci slave window (access: pci -> vme)
135 unsigned int ctl = 0; in tsi148_pci_slave_window() local
138 result = -1; in tsi148_pci_slave_window()
143 if (0x00000000 == readl(&dev->uregs->outbound[i].otat)) in tsi148_pci_slave_window()
149 result = -1; in tsi148_pci_slave_window()
157 __raw_writel(htonl(pciAddr), &dev->uregs->outbound[i].otsal); in tsi148_pci_slave_window()
158 __raw_writel(0x00000000, &dev->uregs->outbound[i].otsau); in tsi148_pci_slave_window()
159 __raw_writel(htonl(pciAddr + size), &dev->uregs->outbound[i].oteal); in tsi148_pci_slave_window()
160 __raw_writel(0x00000000, &dev->uregs->outbound[i].oteau); in tsi148_pci_slave_window()
161 __raw_writel(htonl(vmeAddr - pciAddr), &dev->uregs->outbound[i].otofl); in tsi148_pci_slave_window()
162 __raw_writel(0x00000000, &dev->uregs->outbound[i].otofu); in tsi148_pci_slave_window()
166 ctl = 0x00000000; in tsi148_pci_slave_window()
169 ctl = 0x00000001; in tsi148_pci_slave_window()
172 ctl = 0x00000002; in tsi148_pci_slave_window()
178 ctl |= 0x00000000; in tsi148_pci_slave_window()
181 ctl |= 0x00000010; in tsi148_pci_slave_window()
186 ctl |= 0x00000020; in tsi148_pci_slave_window()
190 ctl |= 0x00000000; in tsi148_pci_slave_window()
193 ctl |= 0x00000040; in tsi148_pci_slave_window()
197 ctl |= 0x80040000; /* enable, no prefetch */ in tsi148_pci_slave_window()
199 __raw_writel(htonl(ctl), &dev->uregs->outbound[i].otat); in tsi148_pci_slave_window()
201 debug("Tsi148: window-addr =%p\n", in tsi148_pci_slave_window()
202 &dev->uregs->outbound[i].otsau); in tsi148_pci_slave_window()
204 i, ntohl(__raw_readl(&dev->uregs->outbound[i].otat))); in tsi148_pci_slave_window()
206 i, ntohl(__raw_readl(&dev->uregs->outbound[i].otsal))); in tsi148_pci_slave_window()
208 i, ntohl(__raw_readl(&dev->uregs->outbound[i].oteal))); in tsi148_pci_slave_window()
210 i, ntohl(__raw_readl(&dev->uregs->outbound[i].otofl))); in tsi148_pci_slave_window()
215 return -result; in tsi148_pci_slave_window()
220 unsigned int ctl = 0; in tsi148_eval_vam() local
224 ctl = 0x00000000; in tsi148_eval_vam()
227 ctl = 0x00000010; in tsi148_eval_vam()
230 ctl = 0x00000020; in tsi148_eval_vam()
235 ctl |= 0x00000001; in tsi148_eval_vam()
238 ctl |= 0x00000002; in tsi148_eval_vam()
241 ctl |= 0x00000003; in tsi148_eval_vam()
246 ctl |= 0x00000008; in tsi148_eval_vam()
248 ctl |= 0x00000004; in tsi148_eval_vam()
250 return ctl; in tsi148_eval_vam()
254 * Create vme slave window (access: vme -> pci)
260 unsigned int ctl = 0; in tsi148_vme_slave_window() local
263 result = -1; in tsi148_vme_slave_window()
268 if (0x00000000 == readl(&dev->uregs->inbound[i].itat)) in tsi148_vme_slave_window()
274 result = -1; in tsi148_vme_slave_window()
280 __raw_writel(htonl(vmeAddr), &dev->uregs->inbound[i].itsal); in tsi148_vme_slave_window()
281 __raw_writel(0x00000000, &dev->uregs->inbound[i].itsau); in tsi148_vme_slave_window()
282 __raw_writel(htonl(vmeAddr + size), &dev->uregs->inbound[i].iteal); in tsi148_vme_slave_window()
283 __raw_writel(0x00000000, &dev->uregs->inbound[i].iteau); in tsi148_vme_slave_window()
284 __raw_writel(htonl(pciAddr - vmeAddr), &dev->uregs->inbound[i].itofl); in tsi148_vme_slave_window()
286 __raw_writel(0xffffffff, &dev->uregs->inbound[i].itofu); in tsi148_vme_slave_window()
288 __raw_writel(0x00000000, &dev->uregs->inbound[i].itofu); in tsi148_vme_slave_window()
290 ctl = tsi148_eval_vam(vam); in tsi148_vme_slave_window()
291 ctl |= 0x80000000; /* enable */ in tsi148_vme_slave_window()
292 __raw_writel(htonl(ctl), &dev->uregs->inbound[i].itat); in tsi148_vme_slave_window()
294 debug("Tsi148: window-addr =%p\n", in tsi148_vme_slave_window()
295 &dev->uregs->inbound[i].itsau); in tsi148_vme_slave_window()
297 i, ntohl(__raw_readl(&dev->uregs->inbound[i].itat))); in tsi148_vme_slave_window()
299 i, ntohl(__raw_readl(&dev->uregs->inbound[i].itsal))); in tsi148_vme_slave_window()
301 i, ntohl(__raw_readl(&dev->uregs->inbound[i].iteal))); in tsi148_vme_slave_window()
303 i, ntohl(__raw_readl(&dev->uregs->inbound[i].itofl))); in tsi148_vme_slave_window()
308 return -result; in tsi148_vme_slave_window()
312 * Create vme slave window (access: vme -> gcsr)
317 unsigned int ctl; in tsi148_vme_gcsr_window() local
324 __raw_writel(htonl(vmeAddr), &dev->uregs->gbal); in tsi148_vme_gcsr_window()
325 __raw_writel(0x00000000, &dev->uregs->gbau); in tsi148_vme_gcsr_window()
327 ctl = tsi148_eval_vam(vam); in tsi148_vme_gcsr_window()
328 ctl |= 0x00000080; /* enable */ in tsi148_vme_gcsr_window()
329 __raw_writel(htonl(ctl), &dev->uregs->gcsrat); in tsi148_vme_gcsr_window()
336 * Create vme slave window (access: vme -> crcsr)
341 unsigned int ctl; in tsi148_vme_crcsr_window() local
348 __raw_writel(htonl(vmeAddr), &dev->uregs->crol); in tsi148_vme_crcsr_window()
349 __raw_writel(0x00000000, &dev->uregs->crou); in tsi148_vme_crcsr_window()
351 ctl = 0x00000080; /* enable */ in tsi148_vme_crcsr_window()
352 __raw_writel(htonl(ctl), &dev->uregs->crat); in tsi148_vme_crcsr_window()
359 * Create vme slave window (access: vme -> crg)
364 unsigned int ctl; in tsi148_vme_crg_window() local
371 __raw_writel(htonl(vmeAddr), &dev->uregs->cbal); in tsi148_vme_crg_window()
372 __raw_writel(0x00000000, &dev->uregs->cbau); in tsi148_vme_crg_window()
374 ctl = tsi148_eval_vam(vam); in tsi148_vme_crg_window()
375 ctl |= 0x00000080; /* enable */ in tsi148_vme_crg_window()
376 __raw_writel(htonl(ctl), &dev->uregs->crgat); in tsi148_vme_crg_window()
409 "(VME->CRG):\n"); in do_tsi148()
414 "(VME->CR/CSR):\n"); in do_tsi148()
424 printf("Tsi148: Configuring VME GCSR Window (VME->GCSR):\n"); in do_tsi148()
429 printf("Tsi148: Configuring VME Slave Window (VME->PCI):\n"); in do_tsi148()
435 printf("Tsi148: Configuring PCI Slave Window (PCI->VME):\n"); in do_tsi148()
451 " - initialize tsi148\n"
453 " - create vme slave window (access: vme->pci)\n"
455 " - create pci slave window (access: pci->vme)\n"
457 " - create vme slave window: (access vme->CRG\n"
459 " - create vme slave window: (access vme->CR/CSR\n"
461 " - create vme slave window: (access vme->GCSR\n"
462 " [vam] = VMEbus Address-Modifier: 01 -> A16 Address Space\n"
463 " 02 -> A24 Address Space\n"
464 " 03 -> A32 Address Space\n"
465 " 04 -> Usr AM Code\n"
466 " 08 -> Supervisor AM Code\n"
467 " 10 -> Data AM Code\n"
468 " 20 -> Program AM Code\n"
469 " [vdw] = VMEbus Maximum Datawidth: 02 -> D16 Data Width\n"
470 " 03 -> D32 Data Width\n"