Lines Matching +full:0 +full:xfff7
43 GPIO_WR(GPIO_RD(0x20) | RTK_DBG_GPIO, 0x20); in rtk_dbg_gpio_set()
50 GPIO_WR(GPIO_RD(0x20) & ~RTK_DBG_GPIO, 0x20); in rtk_dbg_gpio_clr()
57 GPIO_WR(GPIO_RD(0x24) | RTK_DBG_GPIO, 0x24); in rtk_dbg_gpio_init()
69 int timeout = 0; in phy_write()
89 writel(data, eng->run.mdio_base + 0x4); in phy_write()
109 printf("[Wr ]%02d: 0x%04x (%02d:%08x)\n", index, data, in phy_write()
112 PRINTF(FP_LOG, "[Wr ]%02d: 0x%04x (%02d:%08x)\n", index, in phy_write()
122 int timeout = 0; in phy_read()
124 if (index > 0x1f) { in phy_read()
125 printf("invalid PHY register index: 0x%02x\n", index); in phy_read()
127 return 0; in phy_read()
150 read_value = readl(eng->run.mdio_base + 0x4) & GENMASK(15, 0); in phy_read()
172 read_value = readl(eng->run.mdio_base + 0x4) >> 16; in phy_read()
177 printf("[Rd ]%02d: 0x%04x (%02d:%08x)\n", index, read_value, in phy_read()
180 PRINTF(FP_LOG, "[Rd ]%02d: 0x%04x (%02d:%08x)\n", index, in phy_read()
191 printf("[RW ]%02d: clr:0x%04x: set:0x%04x (%02d:%08x)\n", adr, in phy_clrset()
195 "[RW ]%02d: clr:0x%04x: set:0x%04x (%02d:%08x)\n", in phy_clrset()
209 for (index = 0; index < 32; index++) { in phy_dump()
223 for (eng->phy.Adr = 0; eng->phy.Adr < 32; eng->phy.Adr++) { in phy_scan_id()
253 phy_clrset(eng, 0, clr, eng->phy.PHY_00h); in phy_basic_setting()
255 printf("[Set]00: 0x%04x (%02d:%08x)\n", in phy_basic_setting()
259 PRINTF(FP_LOG, "[Set]00: 0x%04x (%02d:%08x)\n", in phy_basic_setting()
268 int timeout = 0; in phy_wait_reset_done()
270 while (phy_read(eng, PHY_REG_BMCR) & 0x8000) { in phy_wait_reset_done()
282 printf("[Clr]00: 0x%04x (%02d:%08x)\n", in phy_wait_reset_done()
286 PRINTF(FP_LOG, "[Clr]00: 0x%04x (%02d:%08x)\n", in phy_wait_reset_done()
300 //phy_clrset(eng, 0, 0x0000, 0x8000 | eng->phy.PHY_00h); in phy_reset()
301 phy_clrset(eng, 0, 0x7140, 0x8000 | eng->phy.PHY_00h); in phy_reset()
302 //phy_write(eng, 0, 0x8000); //clr set//Rst PHY in phy_reset()
313 uint16_t wait_phy_ready = 0; in phy_check_register()
314 uint16_t hit_count = 0; in phy_check_register()
325 hit_count = 0; in phy_check_register()
344 if (eng->run.speed_sel[0]) { in recov_phy_marvell()
349 phy_write(eng, 29, 0x0007); in recov_phy_marvell()
350 phy_clrset(eng, 30, 0x0008, 0x0000); //clr set in recov_phy_marvell()
351 phy_write(eng, 29, 0x0010); in recov_phy_marvell()
352 phy_clrset(eng, 30, 0x0002, 0x0000); //clr set in recov_phy_marvell()
353 phy_write(eng, 29, 0x0012); in recov_phy_marvell()
354 phy_clrset(eng, 30, 0x0001, 0x0000); //clr set in recov_phy_marvell()
371 if ( eng->run.speed_sel[ 0 ] ) { in phy_marvell()
374 phy_write( eng, 18, 0x0000 ); in phy_marvell()
375 phy_clrset( eng, 9, 0x0000, 0x1800 );//clr set in phy_marvell()
380 if ( eng->run.speed_sel[ 0 ] ) { in phy_marvell()
381 phy_write( eng, 29, 0x0007 ); in phy_marvell()
382 phy_clrset( eng, 30, 0x0000, 0x0008 );//clr set in phy_marvell()
383 phy_write( eng, 29, 0x0010 ); in phy_marvell()
384 phy_clrset( eng, 30, 0x0000, 0x0002 );//clr set in phy_marvell()
385 phy_write( eng, 29, 0x0012 ); in phy_marvell()
386 phy_clrset( eng, 30, 0x0000, 0x0001 );//clr set in phy_marvell()
391 phy_check_register ( eng, 17, 0x0400, 0x0400, 1, "wait 88E1111 link-up"); in phy_marvell()
392 // Retry = 0; in phy_marvell()
395 // } while ( !( ( eng->phy.PHY_11h & 0x0400 ) | eng->phy.loopback | ( Retry++ > 20 ) ) ); in phy_marvell()
405 if ( eng->run.speed_sel[ 0 ] ) { in recov_phy_marvell0()
406 phy_write( eng, 22, 0x0006 ); in recov_phy_marvell0()
407 phy_clrset( eng, 16, 0x0020, 0x0000 );//clr set in recov_phy_marvell0()
408 phy_write( eng, 22, 0x0000 ); in recov_phy_marvell0()
417 phy_write( eng, 22, 0x0002 ); in phy_marvell0()
420 if ( eng->phy.PHY_15h & 0x0030 ) { in phy_marvell0()
421 …printf("\n\n[Warning] Page2, Register 21, bit 4~5 must be 0 [Reg15_2:%04x]\n\n", eng->phy.PHY_15h); in phy_marvell0()
422 …OTiming ) PRINTF( FP_IO, "\n\n[Warning] Page2, Register 21, bit 4~5 must be 0 [Reg15_2:%04x]\n\n",… in phy_marvell0()
423 …x_only ) PRINTF( FP_LOG, "\n\n[Warning] Page2, Register 21, bit 4~5 must be 0 [Reg15_2:%04x]\n\n",… in phy_marvell0()
425 phy_write( eng, 21, eng->phy.PHY_15h & 0xffcf ); // Set [5]Rx Dly, [4]Tx Dly to 0 in phy_marvell0()
428 phy_write( eng, 22, 0x0000 ); in phy_marvell0()
434 phy_write( eng, 22, 0x0002 ); in phy_marvell0()
436 if ( eng->run.speed_sel[ 0 ] ) { in phy_marvell0()
437 phy_clrset( eng, 21, 0x6040, 0x0040 );//clr set in phy_marvell0()
440 phy_clrset( eng, 21, 0x6040, 0x2000 );//clr set in phy_marvell0()
443 phy_clrset( eng, 21, 0x6040, 0x0000 );//clr set in phy_marvell0()
445 phy_write( eng, 22, 0x0000 ); in phy_marvell0()
449 if ( eng->run.speed_sel[ 0 ] ) { in phy_marvell0()
450 phy_write( eng, 22, 0x0006 ); in phy_marvell0()
451 phy_clrset( eng, 16, 0x0000, 0x0020 );//clr set in phy_marvell0()
453 phy_write( eng, 22, 0x0000 ); in phy_marvell0()
457 phy_read( eng, 0 ); // v069 in phy_marvell0()
461 phy_check_register ( eng, 17, 0x0400, 0x0400, 1, "wait 88E1310 link-up"); in phy_marvell0()
462 // Retry = 0; in phy_marvell0()
465 // } while ( !( ( eng->phy.PHY_11h & 0x0400 ) | eng->phy.loopback | ( Retry++ > 20 ) ) ); in phy_marvell0()
481 …phy_write( eng, 1, 0x0003 ); //01h[1:0]00 = 10 Mbps, 01 = 100 Mbps, 10 = 1000 Mbps, 11 = Speed is… in recov_phy_marvell1()
494 …//The 88E6176 is switch with 7 Port(P0~P6) and the PHYAdr will be fixed at 0x10~0x16, and only P5/… in phy_marvell1()
499 phy_write( eng, 6, 0x0000 );//06h[5]P5 loopback, 06h[6]P6 loopback in phy_marvell1()
504 … if ( eng->run.speed_sel[ 0 ] ) phy_write( eng, 1, (PHY_01h & 0xfffc) | 0x0002… in phy_marvell1()
505 …e if ( eng->run.speed_sel[ 1 ] ) phy_write( eng, 1, (PHY_01h & 0xfffc) | 0x0001 );//[1:0]00 = 10 … in phy_marvell1()
506 …lse phy_write( eng, 1, (PHY_01h & 0xfffc) );//[1:0]00 = 10 … in phy_marvell1()
507 …if ( eng->run.speed_sel[ 0 ] ) phy_write( eng, 1, 0x0002 );//01h[1:0]00 = 10 Mbps, 01 = 100 … in phy_marvell1()
508 …else if ( eng->run.speed_sel[ 1 ] ) phy_write( eng, 1, 0x0001 );//01h[1:0]00 = 10 Mbps, 01 = 100 … in phy_marvell1()
509 …else phy_write( eng, 1, 0x0000 );//01h[1:0]00 = 10 Mbps, 01 = 100 … in phy_marvell1()
512 … if ( eng->phy.Adr == 21 ) phy_write( eng, 6, 0x0020 );//06h[5]P5 loopback, 06h[6]P6 loopback in phy_marvell1()
513 … else phy_write( eng, 6, 0x0040 );//06h[5]P5 loopback, 06h[6]P6 loopback in phy_marvell1()
526 if ( eng->run.speed_sel[ 0 ] ) { in recov_phy_marvell2()
529 phy_write( eng, 22, 0x0006 ); in recov_phy_marvell2()
530 phy_clrset( eng, 18, 0x0008, 0x0000 );//clr set in recov_phy_marvell2()
531 phy_write( eng, 22, 0x0000 ); in recov_phy_marvell2()
541 phy_write(eng, 22, 0x0002); in phy_marvell2()
551 /* switch to page 0 */ in phy_marvell2()
552 phy_write(eng, 22, 0x0000); in phy_marvell2()
560 phy_write( eng, 22, 0x0012 ); in phy_marvell2()
563 // if ( eng->phy.PHY_14h & 0x0020 ) { in phy_marvell2()
564 if ( ( eng->phy.PHY_14h & 0x003f ) != 0x0010 ) { in phy_marvell2()
569 phy_write( eng, 20, ( eng->phy.PHY_14h & 0xffc0 ) | 0x8010 ); in phy_marvell2()
571 … phy_check_register ( eng, 20, 0x8000, 0x0000, 1, "wait 88E15 10/12/14/18 mode reset"); in phy_marvell2()
574 // } while ( ( (temp_reg & 0x8000) == 0x8000 ) & (Retry++ < 20) ); in phy_marvell2()
578 phy_write( eng, 22, 0x0002 ); in phy_marvell2()
579 if ( eng->run.speed_sel[ 0 ] ) { in phy_marvell2()
580 phy_clrset( eng, 21, 0x2040, 0x0040 );//clr set in phy_marvell2()
583 phy_clrset( eng, 21, 0x2040, 0x2000 );//clr set in phy_marvell2()
586 phy_clrset( eng, 21, 0x2040, 0x0000 );//clr set in phy_marvell2()
588 phy_write( eng, 22, 0x0000 ); in phy_marvell2()
595 if ( !eng->run.speed_sel[ 0 ] ) { in phy_marvell2()
596 … phy_check_register ( eng, 17, 0x0040, 0x0040, 10, "wait 88E15 10/12/14/18 link-up"); in phy_marvell2()
597 … phy_check_register ( eng, 17, 0x0040, 0x0000, 10, "wait 88E15 10/12/14/18 link-up"); in phy_marvell2()
598 … phy_check_register ( eng, 17, 0x0040, 0x0040, 10, "wait 88E15 10/12/14/18 link-up"); in phy_marvell2()
602 if ( eng->run.speed_sel[ 0 ] ) { in phy_marvell2()
605 phy_write( eng, 22, 0x0006 ); in phy_marvell2()
606 phy_clrset( eng, 18, 0x0000, 0x0008 );//clr set in phy_marvell2()
607 phy_write( eng, 22, 0x0000 ); in phy_marvell2()
611 phy_check_register ( eng, 17, 0x0400, 0x0400, 10, "wait 88E15 10/12/14/18 link-up"); in phy_marvell2()
616 // phy_check_register ( eng, 17, 0x0400, 0x0400, 10, "wait 88E15 10/12/14/18 link-up"); in phy_marvell2()
617 //// Retry = 0; in phy_marvell2()
620 //// } while ( !( ( eng->phy.PHY_11h & 0x0400 ) | eng->phy.loopback | ( Retry++ > 20 ) ) ); in phy_marvell2()
634 if ( ( eng->phy.PHY_1ch & 0x0c00 ) != 0x0000 ) { in phy_marvell3()
635 …printf("\n\n[Warning] Register 28, bit 10~11 must be 0 (RGMIIRX Edge-align Mode)[Reg1ch:%04x]\n\n"… in phy_marvell3()
636 eng->phy.PHY_1ch = ( eng->phy.PHY_1ch & 0xf3ff ) | 0x0000; in phy_marvell3()
640 if ( ( eng->phy.PHY_1ch & 0x0c00 ) != 0x0800 ) { in phy_marvell3()
642 eng->phy.PHY_1ch = ( eng->phy.PHY_1ch & 0xf3ff ) | 0x0800; in phy_marvell3()
657 phy_check_register ( eng, 17, 0x0400, 0x0400, 1, "wait 88E3019 link-up"); in phy_marvell3()
668 if ( eng->run.ieee_sel == 0 ) { in phy_broadcom()
669 phy_write( eng, 25, 0x1f01 );//Force MDI //Measuring from channel A in phy_broadcom()
672 phy_clrset( eng, 24, 0x0000, 0x4000 );//clr set//Force Link in phy_broadcom()
673 // phy_write( eng, 0, eng->phy.PHY_00h ); in phy_broadcom()
674 // phy_write( eng, 30, 0x1000 ); in phy_broadcom()
679 // we can check link status from register 0x18 in phy_broadcom()
682 reg = phy_read( eng, 0x18 ) & 0xF; in phy_broadcom()
683 } while ( reg != 0x7 ); in phy_broadcom()
687 reg = phy_read( eng, 0x18 ) & 0xF; in phy_broadcom()
688 } while ( reg != 0x1 ); in phy_broadcom()
695 phy_write( eng, 0, eng->phy.PHY_00h ); in recov_phy_broadcom0()
697 // phy_write( eng, 24, eng->phy.PHY_18h | 0xf007 );//write reg 18h, shadow value 111 in recov_phy_broadcom0()
698 // phy_write( eng, 28, eng->phy.PHY_1ch | 0x8c00 );//write reg 1Ch, shadow value 00011 in recov_phy_broadcom0()
703 phy_write( eng, 0, eng->phy.PHY_00h ); in recov_phy_broadcom0()
722 phy_write( eng, 0, eng->phy.PHY_00h & ~BIT(10)); in phy_broadcom0()
725 * RX interface delay: reg 0x18, shadow value b'0111: misc control in phy_broadcom0()
728 phy_write(eng, 0x18, (0x7 << 12) | 0x7); in phy_broadcom0()
729 eng->phy.PHY_18h = phy_read(eng, 0x18); in phy_broadcom0()
730 PHY_new = eng->phy.PHY_18h & ~((0x7 << 12) | 0x7 | BIT(8)); in phy_broadcom0()
731 PHY_new |= (0x7 << 12) | 0x7 | BIT(15); in phy_broadcom0()
734 phy_write(eng, 0x18, PHY_new); in phy_broadcom0()
737 * TX interface delay: reg 0x1c, shadow value b'0011: clock alignment in phy_broadcom0()
741 phy_write(eng, 0x1c, 0x3 << 10); in phy_broadcom0()
742 eng->phy.PHY_1ch = phy_read(eng, 0x1c); in phy_broadcom0()
743 PHY_new = eng->phy.PHY_1ch & ~((0x1f << 10) | BIT(9)); in phy_broadcom0()
744 PHY_new |= (0x3 << 10) | BIT(15); in phy_broadcom0()
747 phy_write(eng, 0x1c, PHY_new); in phy_broadcom0()
754 if (strncmp((char *)eng->phy.phy_name, "BCM5421x", strlen("BCM5421x")) == 0) in phy_broadcom0()
755 phy_write(eng, 0x1e, BIT(12)); in phy_broadcom0()
757 if (eng->run.speed_sel[0]) { in phy_broadcom0()
758 phy_write(eng, 0x9, 0x1800); in phy_broadcom0()
759 phy_write(eng, 0x0, 0x0140); in phy_broadcom0()
760 phy_write(eng, 0x18, 0x8400); in phy_broadcom0()
762 phy_write(eng, 0x0, 0x2100); in phy_broadcom0()
763 phy_write(eng, 0x18, 0x8400); in phy_broadcom0()
765 phy_write(eng, 0x0, 0x0100); in phy_broadcom0()
766 phy_write(eng, 0x18, 0x8400); in phy_broadcom0()
791 if ( ( eng->phy.PHY_19h & 0x0400 ) == 0x0 ) { in phy_realtek0()
792 phy_write( eng, 25, eng->phy.PHY_19h | 0x0400 ); in phy_realtek0()
798 if ( eng->arg.ctrl.b.rmii_phy_in == 0 ) { in phy_realtek0()
799 if ( ( eng->phy.PHY_19h & 0x0800 ) == 0x0800 ) { in phy_realtek0()
800 phy_write( eng, 25, eng->phy.PHY_19h & 0xf7ff ); in phy_realtek0()
801 …printf("\n\n[Warning] Register 25, bit 11 must be 0 (TXC should be output mode)[Reg19h:%04x]\n\n",… in phy_realtek0()
802 …run.TM_IOTiming ) PRINTF( FP_IO, "\n\n[Warning] Register 25, bit 11 must be 0 (TXC should be outpu… in phy_realtek0()
803 …run.tm_tx_only ) PRINTF( FP_LOG, "\n\n[Warning] Register 25, bit 11 must be 0 (TXC should be outpu… in phy_realtek0()
806 if ( ( eng->phy.PHY_19h & 0x0800 ) == 0x0000 ) { in phy_realtek0()
807 phy_write( eng, 25, eng->phy.PHY_19h | 0x0800 ); in phy_realtek0()
815 phy_write( eng, 31, 0x0001 ); in phy_realtek0()
816 if ( eng->run.ieee_sel == 0 ) { in phy_realtek0()
817 phy_write( eng, 25, 0x1f01 );//Force MDI //Measuring from channel A in phy_realtek0()
820 phy_write( eng, 25, 0x1f00 );//Force MDIX //Measuring from channel B in phy_realtek0()
822 phy_write( eng, 31, 0x0000 ); in phy_realtek0()
830 if ( eng->run.speed_sel[ 0 ] ) { in recov_phy_realtek1()
831 if ( eng->run.ieee_sel == 0 ) {//Test Mode 1 in recov_phy_realtek1()
833 phy_write( eng, 31, 0x0002 ); in recov_phy_realtek1()
834 phy_write( eng, 2, 0xc203 ); in recov_phy_realtek1()
835 phy_write( eng, 31, 0x0000 ); in recov_phy_realtek1()
836 phy_write( eng, 9, 0x0000 ); in recov_phy_realtek1()
840 phy_write( eng, 31, 0x0000 ); in recov_phy_realtek1()
841 phy_write( eng, 9, 0x0000 ); in recov_phy_realtek1()
846 phy_write( eng, 23, 0x2100 ); in recov_phy_realtek1()
847 phy_write( eng, 16, 0x016e ); in recov_phy_realtek1()
851 phy_write( eng, 31, 0x0006 ); in recov_phy_realtek1()
852 phy_write( eng, 0, 0x5a00 ); in recov_phy_realtek1()
853 phy_write( eng, 31, 0x0000 ); in recov_phy_realtek1()
860 if ( eng->run.speed_sel[ 0 ] ) { in recov_phy_realtek1()
861 phy_write( eng, 31, 0x0000 ); // new in Rev. 1.6 in recov_phy_realtek1()
862 phy_write( eng, 0, 0x1140 ); // new in Rev. 1.6 in recov_phy_realtek1()
863 phy_write( eng, 20, 0x8040 ); // new in Rev. 1.6 in recov_phy_realtek1()
867 if ( eng->run.speed_sel[ 0 ] ) { in recov_phy_realtek1()
868 phy_write( eng, 31, 0x0001 ); in recov_phy_realtek1()
869 phy_write( eng, 3, 0xdf41 ); in recov_phy_realtek1()
870 phy_write( eng, 2, 0xdf20 ); in recov_phy_realtek1()
871 phy_write( eng, 1, 0x0140 ); in recov_phy_realtek1()
872 phy_write( eng, 0, 0x00bb ); in recov_phy_realtek1()
873 phy_write( eng, 4, 0xb800 ); in recov_phy_realtek1()
874 phy_write( eng, 4, 0xb000 ); in recov_phy_realtek1()
876 phy_write( eng, 31, 0x0000 ); in recov_phy_realtek1()
877 // phy_write( eng, 26, 0x0020 ); // Rev. 1.2 in recov_phy_realtek1()
878 phy_write( eng, 26, 0x0040 ); // new in Rev. 1.6 in recov_phy_realtek1()
879 phy_write( eng, 0, 0x1140 ); in recov_phy_realtek1()
880 // phy_write( eng, 21, 0x0006 ); // Rev. 1.2 in recov_phy_realtek1()
881 phy_write( eng, 21, 0x1006 ); // new in Rev. 1.6 in recov_phy_realtek1()
882 phy_write( eng, 23, 0x2100 ); in recov_phy_realtek1()
885 // phy_write( eng, 31, 0x0000 ); in recov_phy_realtek1()
886 // phy_write( eng, 9, 0x0200 ); in recov_phy_realtek1()
887 // phy_write( eng, 0, 0x1200 ); in recov_phy_realtek1()
890 // phy_write( eng, 31, 0x0000 ); in recov_phy_realtek1()
891 // phy_write( eng, 9, 0x0200 ); in recov_phy_realtek1()
892 // phy_write( eng, 4, 0x05e1 ); in recov_phy_realtek1()
893 // phy_write( eng, 0, 0x1200 ); in recov_phy_realtek1()
909 if ( eng->run.speed_sel[ 0 ] ) { in phy_realtek1()
910 if ( eng->run.ieee_sel == 0 ) {//Test Mode 1 in phy_realtek1()
912 phy_write( eng, 31, 0x0002 ); in phy_realtek1()
913 phy_write( eng, 2, 0xc22b ); in phy_realtek1()
914 phy_write( eng, 31, 0x0000 ); in phy_realtek1()
915 phy_write( eng, 9, 0x2000 ); in phy_realtek1()
919 phy_write( eng, 31, 0x0000 ); in phy_realtek1()
920 phy_write( eng, 9, 0x8000 ); in phy_realtek1()
924 if ( eng->run.ieee_sel == 0 ) {//From Channel A in phy_realtek1()
926 phy_write( eng, 23, 0xa102 ); in phy_realtek1()
927 phy_write( eng, 16, 0x01ae );//MDI in phy_realtek1()
931 phy_clrset( eng, 17, 0x0008, 0x0000 ); // clr set in phy_realtek1()
932 phy_write( eng, 23, 0xa102 ); // MDI in phy_realtek1()
933 phy_write( eng, 16, 0x010e ); in phy_realtek1()
937 … if ( eng->run.ieee_sel == 0 ) {//Diff. Voltage/TP-IDL/Jitter: Pseudo-random pattern in phy_realtek1()
938 phy_write( eng, 31, 0x0006 ); in phy_realtek1()
939 phy_write( eng, 0, 0x5a21 ); in phy_realtek1()
940 phy_write( eng, 31, 0x0000 ); in phy_realtek1()
943 phy_write( eng, 31, 0x0006 ); in phy_realtek1()
944 phy_write( eng, 2, 0x05ee ); in phy_realtek1()
945 phy_write( eng, 0, 0xff21 ); in phy_realtek1()
946 phy_write( eng, 31, 0x0000 ); in phy_realtek1()
949 phy_write( eng, 31, 0x0006 ); in phy_realtek1()
950 phy_write( eng, 2, 0x05ee ); in phy_realtek1()
951 phy_write( eng, 0, 0x0021 ); in phy_realtek1()
952 phy_write( eng, 31, 0x0000 ); in phy_realtek1()
963 if ( eng->run.speed_sel[ 0 ] ) { in phy_realtek1()
964 phy_write( eng, 20, 0x0042 );//new in Rev. 1.6 in phy_realtek1()
970 if ( eng->run.speed_sel[ 0 ] ) { in phy_realtek1()
971 phy_write( eng, 31, 0x0001 ); in phy_realtek1()
972 phy_write( eng, 3, 0xff41 ); in phy_realtek1()
973 phy_write( eng, 2, 0xd720 ); in phy_realtek1()
974 phy_write( eng, 1, 0x0140 ); in phy_realtek1()
975 phy_write( eng, 0, 0x00bb ); in phy_realtek1()
976 phy_write( eng, 4, 0xb800 ); in phy_realtek1()
977 phy_write( eng, 4, 0xb000 ); in phy_realtek1()
979 phy_write( eng, 31, 0x0007 ); in phy_realtek1()
980 phy_write( eng, 30, 0x0040 ); in phy_realtek1()
981 phy_write( eng, 24, 0x0008 ); in phy_realtek1()
983 phy_write( eng, 31, 0x0000 ); in phy_realtek1()
984 phy_write( eng, 9, 0x0300 ); in phy_realtek1()
985 phy_write( eng, 26, 0x0020 ); in phy_realtek1()
986 phy_write( eng, 0, 0x0140 ); in phy_realtek1()
987 phy_write( eng, 23, 0xa101 ); in phy_realtek1()
988 phy_write( eng, 21, 0x0200 ); in phy_realtek1()
989 phy_write( eng, 23, 0xa121 ); in phy_realtek1()
990 phy_write( eng, 23, 0xa161 ); in phy_realtek1()
991 phy_write( eng, 0, 0x8000 ); in phy_realtek1()
998 // phy_write( eng, 31, 0x0000 ); in phy_realtek1()
999 // phy_write( eng, 9, 0x0000 ); in phy_realtek1()
1000 // phy_write( eng, 4, 0x0061 ); in phy_realtek1()
1001 // phy_write( eng, 0, 0x1200 ); in phy_realtek1()
1005 // phy_write( eng, 31, 0x0000 ); in phy_realtek1()
1006 // phy_write( eng, 9, 0x0000 ); in phy_realtek1()
1007 // phy_write( eng, 4, 0x05e1 ); in phy_realtek1()
1008 // phy_write( eng, 0, 0x1200 ); in phy_realtek1()
1024 if ( eng->run.speed_sel[ 0 ] ) { in recov_phy_realtek2()
1026 phy_write( eng, 31, 0x0000 ); in recov_phy_realtek2()
1027 phy_write( eng, 9, 0x0000 ); in recov_phy_realtek2()
1031 phy_write( eng, 31, 0x0007 ); in recov_phy_realtek2()
1032 phy_write( eng, 30, 0x002f ); in recov_phy_realtek2()
1033 phy_write( eng, 23, 0xd88f ); in recov_phy_realtek2()
1034 phy_write( eng, 30, 0x002d ); in recov_phy_realtek2()
1035 phy_write( eng, 24, 0xf050 ); in recov_phy_realtek2()
1036 phy_write( eng, 31, 0x0000 ); in recov_phy_realtek2()
1037 phy_write( eng, 16, 0x006e ); in recov_phy_realtek2()
1041 phy_write( eng, 31, 0x0006 ); in recov_phy_realtek2()
1042 phy_write( eng, 0, 0x5a00 ); in recov_phy_realtek2()
1043 phy_write( eng, 31, 0x0000 ); in recov_phy_realtek2()
1046 phy_write( eng, 31, 0x0005 ); in recov_phy_realtek2()
1047 phy_write( eng, 5, 0x8b86 ); in recov_phy_realtek2()
1048 phy_write( eng, 6, 0xe201 ); in recov_phy_realtek2()
1049 phy_write( eng, 31, 0x0007 ); in recov_phy_realtek2()
1050 phy_write( eng, 30, 0x0020 ); in recov_phy_realtek2()
1051 phy_write( eng, 21, 0x1108 ); in recov_phy_realtek2()
1052 phy_write( eng, 31, 0x0000 ); in recov_phy_realtek2()
1060 if ( eng->run.speed_sel[ 0 ] ) { in recov_phy_realtek2()
1062 phy_write( eng, 31, 0x0000 ); in recov_phy_realtek2()
1063 phy_write( eng, 0, 0x8000 ); in recov_phy_realtek2()
1070 phy_write( eng, 31, 0x0007 ); in recov_phy_realtek2()
1071 phy_write( eng, 30, 0x0042 ); in recov_phy_realtek2()
1072 phy_write( eng, 21, 0x0500 ); in recov_phy_realtek2()
1073 phy_write( eng, 31, 0x0000 ); in recov_phy_realtek2()
1074 phy_write( eng, 0, 0x1140 ); in recov_phy_realtek2()
1075 phy_write( eng, 26, 0x0040 ); in recov_phy_realtek2()
1076 phy_write( eng, 31, 0x0007 ); in recov_phy_realtek2()
1077 phy_write( eng, 30, 0x002f ); in recov_phy_realtek2()
1078 phy_write( eng, 23, 0xd88f ); in recov_phy_realtek2()
1079 phy_write( eng, 30, 0x0023 ); in recov_phy_realtek2()
1080 phy_write( eng, 22, 0x0300 ); in recov_phy_realtek2()
1081 phy_write( eng, 31, 0x0000 ); in recov_phy_realtek2()
1082 phy_write( eng, 21, 0x1006 ); in recov_phy_realtek2()
1083 phy_write( eng, 23, 0x2100 ); in recov_phy_realtek2()
1086 // phy_write( eng, 31, 0x0000 ); in recov_phy_realtek2()
1087 // phy_write( eng, 9, 0x0200 ); in recov_phy_realtek2()
1088 // phy_write( eng, 0, 0x1200 ); in recov_phy_realtek2()
1091 // phy_write( eng, 31, 0x0000 ); in recov_phy_realtek2()
1092 // phy_write( eng, 9, 0x0200 ); in recov_phy_realtek2()
1093 // phy_write( eng, 4, 0x05e1 ); in recov_phy_realtek2()
1094 // phy_write( eng, 0, 0x1200 ); in recov_phy_realtek2()
1097 phy_write( eng, 31, 0x0000 ); in recov_phy_realtek2()
1098 phy_write( eng, 0, 0x1140 ); in recov_phy_realtek2()
1102 // Check register 0x11 bit10 Link OK or not OK in recov_phy_realtek2()
1103 phy_check_register ( eng, 17, 0x0c02, 0x0000, 10, "clear RTL8211E"); in recov_phy_realtek2()
1125 phy_write( eng, 31, 0x0000 ); in phy_realtek2()
1126 phy_clrset( eng, 0, 0x0000, 0x8000 | eng->phy.PHY_00h ); // clr set // Rst PHY in phy_realtek2()
1134 phy_write( eng, 31, 0x0005 ); in phy_realtek2()
1135 phy_write( eng, 5, 0x8b86 ); in phy_realtek2()
1136 phy_write( eng, 6, 0xe200 ); in phy_realtek2()
1137 phy_write( eng, 31, 0x0007 ); in phy_realtek2()
1138 phy_write( eng, 30, 0x0020 ); in phy_realtek2()
1139 phy_write( eng, 21, 0x0108 ); in phy_realtek2()
1140 phy_write( eng, 31, 0x0000 ); in phy_realtek2()
1142 if ( eng->run.speed_sel[ 0 ] ) { in phy_realtek2()
1144 phy_write( eng, 31, 0x0000 ); in phy_realtek2()
1146 if ( eng->run.ieee_sel == 0 ) { in phy_realtek2()
1147 phy_write( eng, 9, 0x2000 );//Test Mode 1 in phy_realtek2()
1150 phy_write( eng, 9, 0x8000 );//Test Mode 4 in phy_realtek2()
1155 phy_write( eng, 31, 0x0007 ); in phy_realtek2()
1156 phy_write( eng, 30, 0x002f ); in phy_realtek2()
1157 phy_write( eng, 23, 0xd818 ); in phy_realtek2()
1158 phy_write( eng, 30, 0x002d ); in phy_realtek2()
1159 phy_write( eng, 24, 0xf060 ); in phy_realtek2()
1160 phy_write( eng, 31, 0x0000 ); in phy_realtek2()
1162 if ( eng->run.ieee_sel == 0 ) { in phy_realtek2()
1163 phy_write( eng, 16, 0x00ae );//From Channel A in phy_realtek2()
1166 phy_write( eng, 16, 0x008e );//From Channel B in phy_realtek2()
1171 phy_write( eng, 31, 0x0006 ); in phy_realtek2()
1172 if ( eng->run.ieee_sel == 0 ) {//Diff. Voltage/TP-IDL/Jitter in phy_realtek2()
1173 phy_write( eng, 0, 0x5a21 ); in phy_realtek2()
1176 phy_write( eng, 2, 0x05ee ); in phy_realtek2()
1177 phy_write( eng, 0, 0xff21 ); in phy_realtek2()
1180 phy_write( eng, 2, 0x05ee ); in phy_realtek2()
1181 phy_write( eng, 0, 0x0021 ); in phy_realtek2()
1183 phy_write( eng, 31, 0x0000 ); in phy_realtek2()
1193 phy_write( eng, 0, 0x0000 ); in phy_realtek2()
1194 phy_write( eng, 0, 0x8000 ); in phy_realtek2()
1196 phy_write( eng, 0, eng->phy.PHY_00h ); in phy_realtek2()
1201 phy_clrset( eng, 0, 0x0000, 0x8000 | eng->phy.PHY_00h );//clr set//Rst PHY in phy_realtek2()
1211 if ( eng->run.speed_sel[ 0 ] ) { in phy_realtek2()
1212 check_value = 0x0c02 | 0xa000; in phy_realtek2()
1215 check_value = 0x0c02 | 0x6000; in phy_realtek2()
1218 check_value = 0x0c02 | 0x2000; in phy_realtek2()
1221 if ( eng->run.speed_sel[ 0 ] ) { in phy_realtek2()
1222 check_value = 0x0c02 | 0xa000; in phy_realtek2()
1224 phy_write( eng, 31, 0x0000 ); in phy_realtek2()
1225 phy_write( eng, 0, 0x8000 ); in phy_realtek2()
1229 phy_write( eng, 31, 0x0007 ); in phy_realtek2()
1230 phy_write( eng, 30, 0x0042 ); in phy_realtek2()
1231 phy_write( eng, 21, 0x2500 ); in phy_realtek2()
1232 phy_write( eng, 30, 0x0023 ); in phy_realtek2()
1233 phy_write( eng, 22, 0x0006 ); in phy_realtek2()
1234 phy_write( eng, 31, 0x0000 ); in phy_realtek2()
1235 phy_write( eng, 0, 0x0140 ); in phy_realtek2()
1236 phy_write( eng, 26, 0x0060 ); in phy_realtek2()
1237 phy_write( eng, 31, 0x0007 ); in phy_realtek2()
1238 phy_write( eng, 30, 0x002f ); in phy_realtek2()
1239 phy_write( eng, 23, 0xd820 ); in phy_realtek2()
1240 phy_write( eng, 31, 0x0000 ); in phy_realtek2()
1241 phy_write( eng, 21, 0x0206 ); in phy_realtek2()
1242 phy_write( eng, 23, 0x2120 ); in phy_realtek2()
1243 phy_write( eng, 23, 0x2160 ); in phy_realtek2()
1251 // check_value = 0x0c02 | 0x6000; in phy_realtek2()
1252 // phy_write( eng, 31, 0x0000 ); in phy_realtek2()
1253 // phy_write( eng, 9, 0x0000 ); in phy_realtek2()
1254 // phy_write( eng, 4, 0x05e1 ); in phy_realtek2()
1255 // phy_write( eng, 0, 0x1200 ); in phy_realtek2()
1259 // check_value = 0x0c02 | 0x2000; in phy_realtek2()
1260 // phy_write( eng, 31, 0x0000 ); in phy_realtek2()
1261 // phy_write( eng, 9, 0x0000 ); in phy_realtek2()
1262 // phy_write( eng, 4, 0x0061 ); in phy_realtek2()
1263 // phy_write( eng, 0, 0x1200 ); in phy_realtek2()
1268 check_value = 0x0c02 | 0x6000; in phy_realtek2()
1270 check_value = 0x0c02 | 0x2000; in phy_realtek2()
1271 phy_write( eng, 31, 0x0000 ); in phy_realtek2()
1272 phy_write( eng, 0, eng->phy.PHY_00h ); in phy_realtek2()
1282 // Check register 0x11 bit10 Link OK or not OK in phy_realtek2()
1283 phy_check_register ( eng, 17, 0x0c02 | 0xe000, check_value, 10, "set RTL8211E"); in phy_realtek2()
1294 if ( eng->run.speed_sel[ 0 ] ) { in recov_phy_realtek3()
1295 phy_write( eng, 9, 0x0000 ); in recov_phy_realtek3()
1299 phy_write( eng, 14, 0x0000 ); in recov_phy_realtek3()
1300 phy_write( eng, 16, 0x00a0 ); in recov_phy_realtek3()
1303 // phy_write( eng, 31, 0x0006 ); in recov_phy_realtek3()
1304 // phy_write( eng, 0, 0x5a00 ); in recov_phy_realtek3()
1305 // phy_write( eng, 31, 0x0000 ); in recov_phy_realtek3()
1312 if ( eng->run.speed_sel[ 0 ] ) { in recov_phy_realtek3()
1313 phy_write( eng, 11, 0x0000 ); in recov_phy_realtek3()
1315 phy_write( eng, 12, 0x1006 ); in recov_phy_realtek3()
1318 if ( eng->run.speed_sel[ 0 ] ) { in recov_phy_realtek3()
1319 phy_write( eng, 31, 0x0001 ); in recov_phy_realtek3()
1320 phy_write( eng, 4, 0xb000 ); in recov_phy_realtek3()
1321 phy_write( eng, 3, 0xff41 ); in recov_phy_realtek3()
1322 phy_write( eng, 2, 0xdf20 ); in recov_phy_realtek3()
1323 phy_write( eng, 1, 0x0140 ); in recov_phy_realtek3()
1324 phy_write( eng, 0, 0x00bb ); in recov_phy_realtek3()
1325 phy_write( eng, 4, 0xb800 ); in recov_phy_realtek3()
1326 phy_write( eng, 4, 0xb000 ); in recov_phy_realtek3()
1328 phy_write( eng, 31, 0x0000 ); in recov_phy_realtek3()
1329 phy_write( eng, 25, 0x8c00 ); in recov_phy_realtek3()
1330 phy_write( eng, 26, 0x0040 ); in recov_phy_realtek3()
1331 phy_write( eng, 0, 0x1140 ); in recov_phy_realtek3()
1332 phy_write( eng, 14, 0x0000 ); in recov_phy_realtek3()
1333 phy_write( eng, 12, 0x1006 ); in recov_phy_realtek3()
1334 phy_write( eng, 23, 0x2109 ); in recov_phy_realtek3()
1345 if ( eng->run.speed_sel[ 0 ] ) { in phy_realtek3()
1346 if ( eng->run.ieee_sel == 0 ) { //Test Mode 1 in phy_realtek3()
1347 phy_write( eng, 9, 0x2000 ); in phy_realtek3()
1350 phy_write( eng, 9, 0x4000 ); in phy_realtek3()
1353 phy_write( eng, 9, 0x6000 ); in phy_realtek3()
1356 phy_write( eng, 9, 0x8000 ); in phy_realtek3()
1361 phy_write( eng, 17, eng->phy.PHY_11h & 0xfff7 ); in phy_realtek3()
1362 phy_write( eng, 14, 0x0660 ); in phy_realtek3()
1364 if ( eng->run.ieee_sel == 0 ) { in phy_realtek3()
1365 phy_write( eng, 16, 0x00a0 );//MDI //From Channel A in phy_realtek3()
1368 phy_write( eng, 16, 0x0080 );//MDIX //From Channel B in phy_realtek3()
1372 // if ( eng->run.ieee_sel == 0 ) {//Pseudo-random pattern in phy_realtek3()
1373 // phy_write( eng, 31, 0x0006 ); in phy_realtek3()
1374 // phy_write( eng, 0, 0x5a21 ); in phy_realtek3()
1375 // phy_write( eng, 31, 0x0000 ); in phy_realtek3()
1378 // phy_write( eng, 31, 0x0006 ); in phy_realtek3()
1379 // phy_write( eng, 2, 0x05ee ); in phy_realtek3()
1380 // phy_write( eng, 0, 0xff21 ); in phy_realtek3()
1381 // phy_write( eng, 31, 0x0000 ); in phy_realtek3()
1384 // phy_write( eng, 31, 0x0006 ); in phy_realtek3()
1385 // phy_write( eng, 2, 0x05ee ); in phy_realtek3()
1386 // phy_write( eng, 0, 0x0021 ); in phy_realtek3()
1387 // phy_write( eng, 31, 0x0000 ); in phy_realtek3()
1396 phy_write( eng, 0, 0x9200 ); in phy_realtek3()
1400 phy_write( eng, 17, 0x401c ); in phy_realtek3()
1401 phy_write( eng, 12, 0x0006 ); in phy_realtek3()
1403 if ( eng->run.speed_sel[ 0 ] ) { in phy_realtek3()
1404 phy_write( eng, 11, 0x0002 ); in phy_realtek3()
1411 if ( eng->run.speed_sel[ 0 ] ) { in phy_realtek3()
1412 phy_write( eng, 31, 0x0001 ); in phy_realtek3()
1413 phy_write( eng, 4, 0xb000 ); in phy_realtek3()
1414 phy_write( eng, 3, 0xff41 ); in phy_realtek3()
1415 phy_write( eng, 2, 0xd720 ); in phy_realtek3()
1416 phy_write( eng, 1, 0x0140 ); in phy_realtek3()
1417 phy_write( eng, 0, 0x00bb ); in phy_realtek3()
1418 phy_write( eng, 4, 0xb800 ); in phy_realtek3()
1419 phy_write( eng, 4, 0xb000 ); in phy_realtek3()
1421 phy_write( eng, 31, 0x0000 ); in phy_realtek3()
1422 phy_write( eng, 25, 0x8400 ); in phy_realtek3()
1423 phy_write( eng, 26, 0x0020 ); in phy_realtek3()
1424 phy_write( eng, 0, 0x0140 ); in phy_realtek3()
1425 phy_write( eng, 14, 0x0210 ); in phy_realtek3()
1426 phy_write( eng, 12, 0x0200 ); in phy_realtek3()
1427 phy_write( eng, 23, 0x2109 ); in phy_realtek3()
1428 phy_write( eng, 23, 0x2139 ); in phy_realtek3()
1445 phy_write( eng, 31, 0x0007 ); in phy_realtek4()
1448 if ( ( eng->phy.PHY_10h & 0x0008 ) == 0x0 ) { in phy_realtek4()
1449 phy_write( eng, 16, eng->phy.PHY_10h | 0x0008 ); in phy_realtek4()
1455 if ( eng->arg.ctrl.b.rmii_phy_in == 0 ) { in phy_realtek4()
1456 if ( ( eng->phy.PHY_10h & 0x1000 ) == 0x1000 ) { in phy_realtek4()
1457 phy_write( eng, 16, eng->phy.PHY_10h & 0xefff ); in phy_realtek4()
1458 …printf("\n\n[Warning] Page 7 Register 16, bit 12 must be 0 (TXC should be output mode)[Reg10h_7:%0… in phy_realtek4()
1459 …IOTiming ) PRINTF( FP_IO, "\n\n[Warning] Page 7 Register 16, bit 12 must be 0 (TXC should be outpu… in phy_realtek4()
1460 …tx_only ) PRINTF( FP_LOG, "\n\n[Warning] Page 7 Register 16, bit 12 must be 0 (TXC should be outpu… in phy_realtek4()
1463 if ( ( eng->phy.PHY_10h & 0x1000 ) == 0x0000 ) { in phy_realtek4()
1464 phy_write( eng, 16, eng->phy.PHY_10h | 0x1000 ); in phy_realtek4()
1470 phy_write( eng, 31, 0x0000 ); in phy_realtek4()
1475 phy_write( eng, 31, 0x0004 ); in phy_realtek4()
1476 phy_write( eng, 16, 0x4077 ); in phy_realtek4()
1477 phy_write( eng, 21, 0xc5a0 ); in phy_realtek4()
1478 phy_write( eng, 31, 0x0000 ); in phy_realtek4()
1481 phy_write( eng, 0, 0x8000 ); // Reset PHY in phy_realtek4()
1483 phy_write( eng, 24, 0x0310 ); // Disable ALDPS in phy_realtek4()
1485 if ( eng->run.ieee_sel == 0 ) {//From Channel A (RJ45 pair 1, 2) in phy_realtek4()
1486 phy_write( eng, 28, 0x40c2 ); //Force MDI in phy_realtek4()
1489 phy_write( eng, 28, 0x40c0 ); //Force MDIX in phy_realtek4()
1491 phy_write( eng, 0, 0x2100 ); //Force 100M/Full Duplex) in phy_realtek4()
1503 phy_write( eng, 31, 0x0000 ); in phy_realtek4()
1504 phy_write( eng, 0, 0x6100 ); in phy_realtek4()
1505 phy_write( eng, 31, 0x0007 ); in phy_realtek4()
1506 phy_write( eng, 16, 0x1FF8 ); in phy_realtek4()
1507 phy_write( eng, 16, 0x0FF8 ); in phy_realtek4()
1508 phy_write( eng, 31, 0x0000 ); in phy_realtek4()
1512 phy_write( eng, 31, 0x0000 ); in phy_realtek4()
1513 phy_write( eng, 0, 0x4100 ); in phy_realtek4()
1514 phy_write( eng, 31, 0x0007 ); in phy_realtek4()
1515 phy_write( eng, 16, 0x1FF8 ); in phy_realtek4()
1516 phy_write( eng, 16, 0x0FF8 ); in phy_realtek4()
1517 phy_write( eng, 31, 0x0000 ); in phy_realtek4()
1525 phy_write( eng, 31, 0x0000 ); in phy_realtek4()
1526 phy_write( eng, 4, 0x01E1 ); in phy_realtek4()
1527 phy_write( eng, 0, 0x1200 ); in phy_realtek4()
1530 phy_write( eng, 31, 0x0000 ); in phy_realtek4()
1531 phy_write( eng, 4, 0x0061 ); in phy_realtek4()
1532 phy_write( eng, 0, 0x1200 ); in phy_realtek4()
1534 // phy_write( eng, 0, 0x8000 ); in phy_realtek4()
1535 // while ( phy_read( eng, 0 ) != 0x3100 ) {} in phy_realtek4()
1536 // while ( phy_read( eng, 0 ) != 0x3100 ) {} in phy_realtek4()
1537 // phy_write( eng, 0, eng->phy.PHY_00h ); in phy_realtek4()
1541 // Check register 0x1 bit2 Link OK or not OK in phy_realtek4()
1542 phy_check_register ( eng, 1, 0x0004, 0x0004, 10, "set RTL8201F"); in phy_realtek4()
1554 if ( eng->run.speed_sel[ 0 ] ) { in recov_phy_realtek5()
1556 phy_write( eng, 31, 0x0000 ); in recov_phy_realtek5()
1557 phy_write( eng, 9, 0x0000 ); in recov_phy_realtek5()
1561 phy_write( eng, 31, 0x0000 ); in recov_phy_realtek5()
1562 phy_write( eng, 24, 0x2118 );//RGMII in recov_phy_realtek5()
1563 phy_write( eng, 9, 0x0200 ); in recov_phy_realtek5()
1564 phy_write( eng, 0, 0x9200 ); in recov_phy_realtek5()
1569 phy_write( eng, 31, 0x0c80 ); in recov_phy_realtek5()
1570 phy_write( eng, 16, 0x5a00 ); in recov_phy_realtek5()
1571 phy_write( eng, 31, 0x0000 ); in recov_phy_realtek5()
1572 phy_write( eng, 4, 0x01e1 ); in recov_phy_realtek5()
1573 phy_write( eng, 9, 0x0200 ); in recov_phy_realtek5()
1574 phy_write( eng, 0, 0x9200 ); in recov_phy_realtek5()
1584 if ( eng->run.speed_sel[ 0 ] ) { in recov_phy_realtek5()
1586 phy_write( eng, 31, 0x0a43 ); in recov_phy_realtek5()
1587 phy_write( eng, 24, 0x2118 ); in recov_phy_realtek5()
1588 phy_write( eng, 0, 0x1040 ); in recov_phy_realtek5()
1591 // phy_write( eng, 31, 0x0000 ); in recov_phy_realtek5()
1592 // phy_write( eng, 9, 0x0200 ); in recov_phy_realtek5()
1593 // phy_write( eng, 0, 0x1200 ); in recov_phy_realtek5()
1596 // phy_write( eng, 31, 0x0000 ); in recov_phy_realtek5()
1597 // phy_write( eng, 9, 0x0200 ); in recov_phy_realtek5()
1598 // phy_write( eng, 4, 0x01e1 ); in recov_phy_realtek5()
1599 // phy_write( eng, 0, 0x1200 ); in recov_phy_realtek5()
1602 phy_write( eng, 31, 0x0000 ); in recov_phy_realtek5()
1603 phy_write( eng, 0, 0x1040 ); in recov_phy_realtek5()
1608 // Check register 0x1A bit2 Link OK or not OK in recov_phy_realtek5()
1609 phy_write( eng, 31, 0x0a43 ); in recov_phy_realtek5()
1610 phy_check_register ( eng, 26, 0x0004, 0x0000, 10, "clear RTL8211F"); in recov_phy_realtek5()
1611 phy_write( eng, 31, 0x0000 ); in recov_phy_realtek5()
1625 /* select page 0xd08 to configure TX and RX delay */ in phy_realtek5()
1626 phy_write(eng, 0x1f, 0xd08); in phy_realtek5()
1628 /* page 0xd08, reg 0x11[8] TX delay enable */ in phy_realtek5()
1629 reg = phy_read(eng, 0x11); in phy_realtek5()
1634 phy_write(eng, 0x11, reg); in phy_realtek5()
1636 /* page 0xd08, reg 0x15[3] RX delay enable */ in phy_realtek5()
1637 reg = phy_read(eng, 0x15); in phy_realtek5()
1642 phy_write(eng, 0x15, reg); in phy_realtek5()
1644 /* restore page 0 */ in phy_realtek5()
1645 phy_write(eng, 0x1f, 0x0); in phy_realtek5()
1649 if (eng->run.speed_sel[0]) { in phy_realtek5()
1651 phy_write(eng, 31, 0x0000); in phy_realtek5()
1652 if (eng->run.ieee_sel == 0) { // Test Mode 1 in phy_realtek5()
1653 phy_write(eng, 9, 0x0200); in phy_realtek5()
1656 phy_write(eng, 9, 0x0400); in phy_realtek5()
1658 phy_write(eng, 9, 0x0800); in phy_realtek5()
1662 phy_write(eng, 31, 0x0000); in phy_realtek5()
1664 0) { // Output MLT-3 from Channel A in phy_realtek5()
1665 phy_write(eng, 24, 0x2318); in phy_realtek5()
1667 phy_write(eng, 24, 0x2218); in phy_realtek5()
1669 phy_write(eng, 9, 0x0000); in phy_realtek5()
1670 phy_write(eng, 0, 0x2100); in phy_realtek5()
1673 // 0: For Diff. Voltage/TP-IDL/Jitter with EEE in phy_realtek5()
1677 // 4: For Harmonic (all "0" patten) with EEE in phy_realtek5()
1678 // 5: For Harmonic (all "0" patten) without EEE in phy_realtek5()
1679 phy_write(eng, 31, 0x0000); in phy_realtek5()
1680 phy_write(eng, 9, 0x0000); in phy_realtek5()
1681 phy_write(eng, 4, 0x0061); in phy_realtek5()
1682 if ((eng->run.ieee_sel & 0x1) == 0) { // with in phy_realtek5()
1684 phy_write(eng, 25, 0x0853); in phy_realtek5()
1686 phy_write(eng, 25, 0x0843); in phy_realtek5()
1688 phy_write(eng, 0, 0x9200); in phy_realtek5()
1691 if ((eng->run.ieee_sel & 0x6) == in phy_realtek5()
1692 0) { // For Diff. Voltage/TP-IDL/Jitter in phy_realtek5()
1693 phy_write(eng, 31, 0x0c80); in phy_realtek5()
1694 phy_write(eng, 18, 0x0115); in phy_realtek5()
1695 phy_write(eng, 16, 0x5a21); in phy_realtek5()
1696 } else if ((eng->run.ieee_sel & 0x6) == in phy_realtek5()
1697 0x2) { // For Harmonic (all "1" in phy_realtek5()
1699 phy_write(eng, 31, 0x0c80); in phy_realtek5()
1700 phy_write(eng, 18, 0x0015); in phy_realtek5()
1701 phy_write(eng, 16, 0xff21); in phy_realtek5()
1702 } else { // For Harmonic (all "0" patten) in phy_realtek5()
1703 phy_write(eng, 31, 0x0c80); in phy_realtek5()
1704 phy_write(eng, 18, 0x0015); in phy_realtek5()
1705 phy_write(eng, 16, 0x0021); in phy_realtek5()
1707 phy_write(eng, 31, 0x0000); in phy_realtek5()
1715 if (eng->run.speed_sel[0]) { in phy_realtek5()
1716 check_value = 0x0004 | 0x0028; in phy_realtek5()
1718 phy_write(eng, 31, 0x0a43); in phy_realtek5()
1719 phy_write(eng, 0, 0x8000); in phy_realtek5()
1727 phy_write(eng, 0, 0x0140); in phy_realtek5()
1728 phy_write(eng, 24, 0x2d18); in phy_realtek5()
1736 check_value = 0x0004 | 0x0018; in phy_realtek5()
1738 check_value = 0x0004 | 0x0008; in phy_realtek5()
1741 phy_write(eng, 31, 0x0a43); in phy_realtek5()
1742 phy_write(eng, 0, 0x8000); in phy_realtek5()
1747 phy_write(eng, 31, 0x0000); in phy_realtek5()
1748 phy_write(eng, 0, eng->phy.PHY_00h); in phy_realtek5()
1758 // Check register 0x1A bit2 Link OK or not OK in phy_realtek5()
1759 phy_write(eng, 31, 0x0a43); in phy_realtek5()
1760 phy_check_register(eng, 26, 0x0004 | 0x0038, check_value, 10, in phy_realtek5()
1762 phy_write(eng, 31, 0x0000); in phy_realtek5()
1783 phy_clrset(eng, 0, 0x0000, in phy_realtek6()
1784 0x8000 | eng->phy.PHY_00h); // clr set//Rst PHY in phy_realtek6()
1807 // phy_write( eng, 24, 0x0600 ); in phy_micrel()
1815 //Reg1Fh[7] = 0(default): 25MHz Mode, XI, XO(pin 9, 8) is 25MHz(crystal/oscilator). in phy_micrel0()
1818 …if ( eng->phy.PHY_1fh & 0x0080 ) sprintf((char *)eng->phy.phy_name, "%s-50MHz Mode", eng->phy.phy_… in phy_micrel0()
1822 phy_clrset( eng, 0, 0x0000, 0x8000 | eng->phy.PHY_00h );//clr set//Rst PHY in phy_micrel0()
1825 phy_clrset( eng, 31, 0x0000, 0x2000 );//clr set//1Fh[13] = 1: Disable auto MDI/MDI-X in phy_micrel0()
1827 phy_clrset( eng, 31, 0x0000, 0x0800 );//clr set//1Fh[11] = 1: Force link pass in phy_micrel0()
1836 phy_clrset( eng, 22, 0x0000, 0x0042 );//clr set in phy_micrel0()
1839 if ( eng->phy.PHY_1fh & 0x0080 ) in phy_micrel0()
1840 phy_clrset( eng, 31, 0x0000, 0x0080 );//clr set//Reset PHY will clear Reg1Fh[7] in phy_micrel0()
1855 phy_write( eng, 13, 0x0002 ); in phy_micrel1()
1856 phy_write( eng, 14, 0x0004 ); in phy_micrel1()
1857 phy_write( eng, 13, 0x4002 ); in phy_micrel1()
1860 phy_write( eng, 14, temp & 0xff0f | 0x0000 ); in phy_micrel1()
1861 // phy_write( eng, 14, temp & 0xff0f | 0x00f0 ); in phy_micrel1()
1864 phy_write( eng, 13, 0x0002 ); in phy_micrel1()
1865 phy_write( eng, 14, 0x0005 ); in phy_micrel1()
1866 phy_write( eng, 13, 0x4002 ); in phy_micrel1()
1871 //Reg2.5[ 3: 0]: RXD0 Pad Skew in phy_micrel1()
1872 phy_write( eng, 14, 0x0000 ); in phy_micrel1()
1873 // phy_write( eng, 14, 0xffff ); in phy_micrel1()
1876 phy_write( eng, 13, 0x0002 ); in phy_micrel1()
1877 phy_write( eng, 14, 0x0008 ); in phy_micrel1()
1878 phy_write( eng, 13, 0x4002 ); in phy_micrel1()
1881 //Reg2.8[4:0]: RX_CLK Pad Skew in phy_micrel1()
1882 // phy_write( eng, 14, temp & 0xffe0 | 0x0000 ); in phy_micrel1()
1883 phy_write( eng, 14, temp & 0xffe0 | 0x001f ); in phy_micrel1()
1899 if ( eng->run.speed_sel[ 0 ] ) { in phy_micrel1()
1946 if ( eng->run.speed_sel[ 0 ] ) { in recov_phy_vitesse()
1969 if ( eng->run.speed_sel[ 0 ] ) { in phy_vitesse()
1975 phy_write( eng, 24, eng->phy.PHY_18h | 0x0001 ); in phy_vitesse()
1976 phy_write( eng, 18, eng->phy.PHY_12h | 0x0020 ); in phy_vitesse()
1993 eng, 11, 0x0000, in recov_phy_atheros()
1994 0x8000); // clr set//Disable hibernate: Reg0Bh[15] = 0 in recov_phy_atheros()
1996 eng, 17, 0x0001, in recov_phy_atheros()
1997 0x0000); // clr set//Enable external loopback: Reg11h[0] = 1 in recov_phy_atheros()
2005 phy_write(eng, 29, 0x000b); in phy_atheros()
2007 if (eng->phy.PHY_1eh & 0x8000) { in phy_atheros()
2009 "be 0 [%04x]\n\n", in phy_atheros()
2014 "15 must be 0 [%04x]\n\n", in phy_atheros()
2019 "15 must be 0 [%04x]\n\n", in phy_atheros()
2022 phy_write(eng, 30, eng->phy.PHY_1eh & 0x7fff); in phy_atheros()
2024 // phy_write( eng, 30, (eng->phy.PHY_1eh & 0x7fff) | 0x8000 ); in phy_atheros()
2027 phy_write(eng, 29, 0x0000); in phy_atheros()
2029 if (eng->phy.PHY_1eh & 0x8000) { in phy_atheros()
2030 printf("\n\n[Warning] Debug register offset = 0, bit 15 must " in phy_atheros()
2031 "be 0 [%04x]\n\n", in phy_atheros()
2035 "\n\n[Warning] Debug register offset = 0, bit " in phy_atheros()
2036 "15 must be 0 [%04x]\n\n", in phy_atheros()
2040 "\n\n[Warning] Debug register offset = 0, bit " in phy_atheros()
2041 "15 must be 0 [%04x]\n\n", in phy_atheros()
2044 phy_write(eng, 30, eng->phy.PHY_1eh & 0x7fff); in phy_atheros()
2046 // phy_write( eng, 30, (eng->phy.PHY_1eh & 0x7fff) | 0x8000 ); in phy_atheros()
2049 phy_write(eng, 29, 0x0005); in phy_atheros()
2051 if (eng->phy.PHY_1eh & 0x0100) { in phy_atheros()
2053 "0 [%04x]\n\n", in phy_atheros()
2058 "must be 0 [%04x]\n\n", in phy_atheros()
2063 "must be 0 [%04x]\n\n", in phy_atheros()
2066 phy_write(eng, 30, eng->phy.PHY_1eh & 0xfeff); in phy_atheros()
2068 // phy_write( eng, 30, (eng->phy.PHY_1eh & 0xfeff) | 0x0100 ); in phy_atheros()
2071 phy_write(eng, 13, 0x0007); in phy_atheros()
2072 phy_write(eng, 14, 0x8016); in phy_atheros()
2073 phy_write(eng, 13, 0x4007); in phy_atheros()
2075 if ((eng->phy.PHY_0eh & 0x0018) != 0x0018) { in phy_atheros()
2077 "0x8016, bit 4~3 must be 3 [%04x]\n\n", in phy_atheros()
2082 "ofset = 0x8016, bit 4~3 must be 3 [%04x]\n\n", in phy_atheros()
2087 "ofset = 0x8016, bit 4~3 must be 3 [%04x]\n\n", in phy_atheros()
2092 phy_write(eng, 14, (eng->phy.PHY_0eh & 0xffe7) | 0x0018); in phy_atheros()
2097 phy_write(eng, 0, eng->phy.PHY_00h); in phy_atheros()
2099 phy_write(eng, 0, eng->phy.PHY_00h); in phy_atheros()
2102 phy_write(eng, 0, eng->phy.PHY_00h); in phy_atheros()
2105 eng, 11, 0x8000, in phy_atheros()
2106 0x0000); // clr set//Disable hibernate: Reg0Bh[15] = 0 in phy_atheros()
2108 eng, 17, 0x0000, in phy_atheros()
2109 0x0001); // clr set//Enable external loopback: Reg11h[0] = 1 in phy_atheros()
2111 phy_write(eng, 0, eng->phy.PHY_00h | 0x8000); in phy_atheros()
2130 * @return 1->addr found, 0->else
2135 uint32_t ret = 0; in phy_find_addr()
2144 if ((ret == 0) && (eng->arg.ctrl.b.skip_phy_id_check)) { in phy_find_addr()
2146 if ((value & BIT(15)) && (0 == eng->arg.ctrl.b.skip_phy_init)) { in phy_find_addr()
2155 if (ret == 0) { in phy_find_addr()
2156 for (eng->phy.Adr = 0; eng->phy.Adr < 32; eng->phy.Adr++) { in phy_find_addr()
2165 if (ret == 0) in phy_find_addr()
2168 if (0 == eng->arg.ctrl.b.skip_phy_init) { in phy_find_addr()
2184 if (0 == eng->arg.ctrl.b.skip_phy_id_check) { in phy_find_addr()
2185 if ((value == 0) || (value == 0xffffffff)) { in phy_find_addr()
2187 if (0 == eng->arg.ctrl.b.skip_phy_init) in phy_find_addr()
2202 if (eng->run.speed_sel[0]) in phy_set00h()
2222 return 0; in phy_check_id()
2239 for (i = 0; i < PHY_LOOKUP_N; i++) { in phy_select()