55 		.base_reset_assert = 0x40, .bit_reset_assert = BIT(11),
56 		.base_reset_deassert = 0x44,.bit_reset_deassert = BIT(11),
57 		.base_clk_stop = 0x80, .bit_clk_stop = BIT(20),
58 		.base_clk_start = 0x84, .bit_clk_start = BIT(20),
61 		.base_reset_assert = 0x40, .bit_reset_assert = BIT(12),
62 		.base_reset_deassert = 0x44,.bit_reset_deassert = BIT(12),
63 		.base_clk_stop = 0x80, .bit_clk_stop = BIT(21),
64 		.base_clk_start = 0x84,.bit_clk_start = BIT(21),
67 		.base_reset_assert = 0x50, .bit_reset_assert = BIT(20),
68 		.base_reset_deassert = 0x54,.bit_reset_deassert = BIT(20),
69 		.base_clk_stop = 0x90, .bit_clk_stop = BIT(20),
70 		.base_clk_start = 0x94, .bit_clk_start = BIT(20),
73 		.base_reset_assert = 0x50, .bit_reset_assert = BIT(21),
74 		.base_reset_deassert = 0x54,.bit_reset_deassert = BIT(21),
75 		.base_clk_stop = 0x90, .bit_clk_stop = BIT(21),
76 		.base_clk_start = 0x94,.bit_clk_start = BIT(21),
84 		.base_reset_assert = 0x04, .bit_reset_assert = BIT(11),
85 		.base_reset_deassert = 0x04, .bit_reset_deassert = BIT(11),
86 		.base_clk_stop = 0x0c, .bit_clk_stop = BIT(20),
87 		.base_clk_start = 0x0c, .bit_clk_start = BIT(20),
90 		.base_reset_assert = 0x04, .bit_reset_assert = BIT(12),
91 		.base_reset_deassert = 0x04, .bit_reset_deassert = BIT(12),
92 		.base_clk_stop = 0x0c, .bit_clk_stop = BIT(21),
93 		.base_clk_start = 0x0c, .bit_clk_start = BIT(21),
100 	if (p_eng->run.speed_sel[0]) {  in Print_Header()
109 	case 0:   in Print_Header()
125 		PRINTF(option, "TX frame - 0x%08x\n", p_eng->arg.user_def_val);  in Print_Header()
135 		printf("%20s| 0: NCSI configuration with    "  in print_arg_test_mode()
144 		printf("%20s| 0: TX/RX delay margin check\n", "");  in print_arg_test_mode()
149 		printf("%20s| 5: TX frame - user defined (default:0x%8x)\n", "",  in print_arg_test_mode()
158 	printf("%20s| 0~31: PHY Address (default:%d)\n", item, DEF_GPHY_ADR);  in print_arg_phy_addr()
165 	printf("%20s| 0/1/2 (default:0)  only for test_mode 3,4,5)\n", item);  in print_arg_ieee_select()
172 	printf("%20s| 1/2/3/... (default:%d) only for test_mode 0\n", item,  in print_arg_delay_scan_range()
206 	printf("%20s| default  : 0x%03x\n", item, DEF_GCTRL);  in print_arg_ctrl()
231 	printf("%20s| bit[0]->1G  bit[1]->100M  bit[2]->10M "  in print_arg_speed()
232 	       "(default:0x%02lx)\n",  in print_arg_speed()
240 	printf("%20s| 0->MDIO1 1->MDIO2", item);  in print_arg_mdio_idx()
252 	printf("%20s| 0->MAC1 1->MAC2", item);  in print_arg_mac_idx()
316 	p_eng->reg.maccr.w = mac_reg_read(p_eng, 0x50);  in push_reg()
318 	p_eng->reg.mac_madr = mac_reg_read(p_eng, 0x08);  in push_reg()
319 	p_eng->reg.mac_ladr = mac_reg_read(p_eng, 0x0c);  in push_reg()
320 	p_eng->reg.mac_fear = mac_reg_read(p_eng, 0x40);  in push_reg()
341 	mac_reg_write(p_eng, 0x50, p_eng->reg.maccr.w);  in pop_reg()
342 	mac_reg_write(p_eng, 0x08, p_eng->reg.mac_madr);  in pop_reg()
343 	mac_reg_write(p_eng, 0x0c, p_eng->reg.mac_ladr);  in pop_reg()
344 	mac_reg_write(p_eng, 0x40, p_eng->reg.mac_fear);  in pop_reg()
396 		return (0);  in finish_check()
404 		case 0:  in check_test_mode()
414 			p_eng->run.TM_NCSI_DiSChannel = 0;  in check_test_mode()
423 		case 0:  in check_test_mode()
434 			p_eng->run.TM_RxDataEn = 0;  in check_test_mode()
436 			p_eng->run.TM_IEEE = 0;  in check_test_mode()
440 			p_eng->run.TM_RxDataEn = 0;  in check_test_mode()
451 	if (0 == p_eng->run.TM_IOStrength) {  in check_test_mode()
452 		p_eng->io.drv_upper_bond = 0;  in check_test_mode()
454 	return 0;  in check_test_mode()
464  *                       = 0 --> MAC#1 reset de-assert
479 	debug("MAC%d:reset assert=0x%02x[%08x] deassert=0x%02x[%08x]\n",  in scu_disable_mac()
482 	debug("MAC%d:clock stop=0x%02x[%08x] start=0x%02x[%08x]\n", mac_idx,  in scu_disable_mac()
487 	debug("reset reg: 0x%08x\n", reg);  in scu_disable_mac()
489 	debug("reset reg: 0x%08x\n", reg);  in scu_disable_mac()
495 	debug("clock reg: 0x%08x\n", reg);  in scu_disable_mac()
497 	debug("clock reg: 0x%08x\n", reg);  in scu_disable_mac()
509 	debug("MAC%d:reset assert=0x%02x[%08x] deassert=0x%02x[%08x]\n",  in scu_enable_mac()
512 	debug("MAC%d:clock stop=0x%02x[%08x] start=0x%02x[%08x]\n", mac_idx,  in scu_enable_mac()
518 	debug("reset reg: 0x%08x\n", reg);  in scu_enable_mac()
520 	debug("reset reg: 0x%08x\n", reg);  in scu_enable_mac()
526 	debug("clock reg: 0x%08x\n", reg);  in scu_enable_mac()
528 	debug("clock reg: 0x%08x\n", reg);  in scu_enable_mac()
534 	SCU_WR(BIT(3), 0x54);  in scu_enable_mac()
537 	debug("reset reg: 0x%08x\n", reg);  in scu_enable_mac()
539 	debug("reset reg: 0x%08x\n", reg);  in scu_enable_mac()
543 	debug("clock reg: 0x%08x\n", reg);  in scu_enable_mac()
545 	debug("clock reg: 0x%08x\n", reg);  in scu_enable_mac()
562 	case 0:  in scu_set_pinmux()
563 		reg = SCU_RD(0x430) | GENMASK(17, 16);  in scu_set_pinmux()
564 		SCU_WR(reg, 0x430);  in scu_set_pinmux()
567 		reg = SCU_RD(0x470) & ~GENMASK(13, 12);  in scu_set_pinmux()
568 		SCU_WR(reg, 0x470);  in scu_set_pinmux()
569 		reg = SCU_RD(0x410) | GENMASK(13, 12);  in scu_set_pinmux()
570 		SCU_WR(reg, 0x410);  in scu_set_pinmux()
573 		reg = SCU_RD(0x470) & ~GENMASK(1, 0);  in scu_set_pinmux()
574 		SCU_WR(reg, 0x470);  in scu_set_pinmux()
575 		reg = SCU_RD(0x410) | GENMASK(1, 0);  in scu_set_pinmux()
576 		SCU_WR(reg, 0x410);  in scu_set_pinmux()
579 		reg = SCU_RD(0x470) & ~GENMASK(3, 2);  in scu_set_pinmux()
580 		SCU_WR(reg, 0x470);  in scu_set_pinmux()
581 		reg = SCU_RD(0x410) | GENMASK(3, 2);  in scu_set_pinmux()
582 		SCU_WR(reg, 0x410);  in scu_set_pinmux()
590 	case 0:  in scu_set_pinmux()
592 		setbits_le32(SCU_BASE + 0x410, BIT(4));  in scu_set_pinmux()
594 		setbits_le32(SCU_BASE + 0x400, GENMASK(11, 0));  in scu_set_pinmux()
595 		setbits_le32(SCU_BASE + 0x410, BIT(4));  in scu_set_pinmux()
596 		clrbits_le32(SCU_BASE + 0x470, BIT(4));  in scu_set_pinmux()
600 		setbits_le32(SCU_BASE + 0x400, GENMASK(23, 12));  in scu_set_pinmux()
601 		setbits_le32(SCU_BASE + 0x410, BIT(5));  in scu_set_pinmux()
602 		clrbits_le32(SCU_BASE + 0x470, BIT(5));  in scu_set_pinmux()
605 		setbits_le32(SCU_BASE + 0x410, GENMASK(27, 16));  in scu_set_pinmux()
606 		setbits_le32(SCU_BASE + 0x410, BIT(6));  in scu_set_pinmux()
607 		clrbits_le32(SCU_BASE + 0x470, BIT(6));  in scu_set_pinmux()
610 		clrbits_le32(SCU_BASE + 0x410, GENMASK(31, 28));  in scu_set_pinmux()
611 		setbits_le32(SCU_BASE + 0x4b0, GENMASK(31, 28));  in scu_set_pinmux()
612 		clrbits_le32(SCU_BASE + 0x474, GENMASK(7, 0));  in scu_set_pinmux()
613 		clrbits_le32(SCU_BASE + 0x414, GENMASK(7, 0));  in scu_set_pinmux()
614 		setbits_le32(SCU_BASE + 0x4b4, GENMASK(7, 0));  in scu_set_pinmux()
615 		setbits_le32(SCU_BASE + 0x410, BIT(7));  in scu_set_pinmux()
616 		clrbits_le32(SCU_BASE + 0x470, BIT(7));  in scu_set_pinmux()
621 	debug("SCU410: %08x %08x %08x %08x\n", SCU_RD(0x410), SCU_RD(0x414), SCU_RD(0x418), SCU_RD(0x41c));  in scu_set_pinmux()
622 	debug("SCU430: %08x %08x %08x %08x\n", SCU_RD(0x430), SCU_RD(0x434), SCU_RD(0x438), SCU_RD(0x43c));  in scu_set_pinmux()
623 	debug("SCU470: %08x %08x %08x %08x\n", SCU_RD(0x470), SCU_RD(0x474), SCU_RD(0x478), SCU_RD(0x47c));  in scu_set_pinmux()
624 	debug("SCU4b0: %08x %08x %08x %08x\n", SCU_RD(0x4b0), SCU_RD(0x4b4), SCU_RD(0x4b8), SCU_RD(0x4bc));  in scu_set_pinmux()
627 	if (p_eng->run.mdio_idx == 0) {  in scu_set_pinmux()
646 	return 0;  in check_mac_idx()
680 	if (0 != check_mac_idx(p_eng)) {  in setup_running()
706 			printf("\nbefore: SCU510=%08x\n", SCU_RD(0x510));  in setup_running()
707 			strap2.w = 0;  in setup_running()
713 			SCU_WR(strap2.w, 0x514);  in setup_running()
714 			while (SCU_RD(0x510) & strap2.w);  in setup_running()
715 			printf("\nafter: SCU510=%08x\n", SCU_RD(0x510));  in setup_running()
728 	for (i = 0; i < 3; i++) {  in setup_running()
750 		if (p_eng->arg.ctrl.w & 0xfffc0000) {  in setup_running()
761 		if (0 == p_eng->arg.loop_max) {  in setup_running()
782 	if (0 != check_test_mode(p_eng)) {  in setup_running()
788 		p_eng->run.delay_margin = 0;  in setup_running()
790 		p_eng->run.ieee_sel = 0;			  in setup_running()
792 #if 0  in setup_running()
793 		if (p_eng->run.delay_margin == 0) {  in setup_running()
802 		p_eng->run.speed_cfg[ 0 ] = 0;  in setup_running()
804 	p_eng->run.tdes_base = (uint32_t)(&tdes_buf[0]);  in setup_running()
805 	p_eng->run.rdes_base = (uint32_t)(&rdes_buf[0]);  in setup_running()
810 		p_eng->run.IO_MrgChk = 0;  in setup_running()
831 		    (p_eng->arg.test_mode == 0))  in setup_running()
893 	return 0;  in setup_running()
905 	strap1.w = SCU_RD(0x500);  in setup_interface()
906 	strap2.w = SCU_RD(0x510);  in setup_interface()
908 	p_eng->env.is_1g_valid[0] = strap1.b.mac1_interface;  in setup_interface()
914 	    p_eng->env.is_1g_valid[0] | p_eng->env.is_1g_valid[1] |  in setup_interface()
918 	strap1.w = SCU_RD(0x70);  in setup_interface()
919 	p_eng->env.is_1g_valid[0] = strap1.b.mac1_interface;  in setup_interface()
923 	    p_eng->env.is_1g_valid[0] | p_eng->env.is_1g_valid[1];  in setup_interface()
925 	return 0;  in setup_interface()
937 	p_eng->env.ast2600 = 0;  in setup_chip_compatibility()
938 	p_eng->env.ast2500 = 0;  in setup_chip_compatibility()
941 	reg_addr = 0x04;  in setup_chip_compatibility()
943 	reg_addr = 0x7c;  in setup_chip_compatibility()
945 	is_valid = 0;  in setup_chip_compatibility()
950 	id = 0x5;  in setup_chip_compatibility()
952 	if (id == 0x5) {  in setup_chip_compatibility()
957 		p_eng->env.is_new_mdio_reg[0] = 1;  in setup_chip_compatibility()
962 	} else if (id == 0x4) {  in setup_chip_compatibility()
966 		p_eng->env.is_new_mdio_reg[0] = MAC1_RD(0x40) >> 31;  in setup_chip_compatibility()
967 		p_eng->env.is_new_mdio_reg[1] = MAC2_RD(0x40) >> 31;  in setup_chip_compatibility()
971 	if (0 == is_valid) {  in setup_chip_compatibility()
976 	return 0;  in setup_chip_compatibility()
984 	if (0 != setup_chip_compatibility(p_eng)) {  in setup_env()
989 	return 0;  in setup_env()
994 	memset(p_eng, 0, sizeof(MAC_ENGINE));  in init_mac_engine()
996 	if (0 != setup_env(p_eng)) {  in init_mac_engine()
1008 		p_eng->arg.ctrl.w = 0;  in init_mac_engine()
1013 		p_eng->arg.loop_inf = 0;  in init_mac_engine()
1014 		p_eng->arg.loop_max = 0;  in init_mac_engine()
1031 	p_eng->io.mac12_1g_delay.addr = SCU_BASE + 0x340;  in init_mac_engine()
1032 	p_eng->io.mac12_1g_delay.tx_min = 0;  in init_mac_engine()
1036 	p_eng->io.mac12_1g_delay.rmii_tx_min = 0;  in init_mac_engine()
1038 	p_eng->io.mac12_1g_delay.rmii_rx_min = 0;  in init_mac_engine()
1041 	p_eng->io.mac12_100m_delay.addr = SCU_BASE + 0x348;  in init_mac_engine()
1042 	p_eng->io.mac12_100m_delay.tx_min = 0;  in init_mac_engine()
1046 	p_eng->io.mac12_10m_delay.addr = SCU_BASE + 0x34c;  in init_mac_engine()
1047 	p_eng->io.mac12_10m_delay.tx_min = 0;  in init_mac_engine()
1052 	p_eng->io.mac34_1g_delay.addr = SCU_BASE + 0x350;  in init_mac_engine()
1053 	p_eng->io.mac34_1g_delay.tx_min = 0;  in init_mac_engine()
1057 	p_eng->io.mac34_1g_delay.rmii_tx_min = 0;  in init_mac_engine()
1059 	p_eng->io.mac34_1g_delay.rmii_rx_min = 0;  in init_mac_engine()
1061 	p_eng->io.mac34_100m_delay.addr = SCU_BASE + 0x358;  in init_mac_engine()
1062 	p_eng->io.mac34_100m_delay.tx_min = 0;  in init_mac_engine()
1066 	p_eng->io.mac34_10m_delay.addr = SCU_BASE + 0x35c;  in init_mac_engine()
1067 	p_eng->io.mac34_10m_delay.tx_min = 0;  in init_mac_engine()
1072 	p_eng->io.mac34_drv_reg.addr = SCU_BASE + 0x458;  in init_mac_engine()
1073 	p_eng->io.mac34_drv_reg.drv_max = 0x3;  in init_mac_engine()
1074 	p_eng->io.drv_upper_bond = 0x3;  in init_mac_engine()
1075 	p_eng->io.drv_lower_bond = 0;  in init_mac_engine()
1077 	p_eng->io.mac12_1g_delay.addr = SCU_BASE + 0x48;  in init_mac_engine()
1078 	p_eng->io.mac12_1g_delay.tx_min = 0;  in init_mac_engine()
1080 	p_eng->io.mac12_1g_delay.rx_min = 0;  in init_mac_engine()
1082 	p_eng->io.mac12_1g_delay.rmii_tx_min = 0;  in init_mac_engine()
1084 	p_eng->io.mac12_1g_delay.rmii_rx_min = 0;  in init_mac_engine()
1086 	p_eng->io.mac12_100m_delay.addr = SCU_BASE + 0xb8;  in init_mac_engine()
1087 	p_eng->io.mac12_100m_delay.tx_min = 0;  in init_mac_engine()
1089 	p_eng->io.mac12_100m_delay.rx_min = 0;  in init_mac_engine()
1091 	p_eng->io.mac12_10m_delay.addr = SCU_BASE + 0xbc;  in init_mac_engine()
1092 	p_eng->io.mac12_10m_delay.tx_min = 0;  in init_mac_engine()
1094 	p_eng->io.mac12_10m_delay.rx_min = 0;  in init_mac_engine()
1097 	p_eng->io.mac34_1g_delay.addr = 0;  in init_mac_engine()
1098 	p_eng->io.mac34_100m_delay.addr = 0;  in init_mac_engine()
1099 	p_eng->io.mac34_10m_delay.addr = 0;  in init_mac_engine()
1101 	p_eng->io.mac12_drv_reg.addr = SCU_BASE + 0x90;  in init_mac_engine()
1102 	p_eng->io.mac12_drv_reg.drv_max = 0x1;  in init_mac_engine()
1103 	p_eng->io.drv_upper_bond = 0x1;  in init_mac_engine()
1104 	p_eng->io.drv_lower_bond = 0;  in init_mac_engine()
1106 	return 0;  in init_mac_engine()
1131 		printf("ctrl=0x%05x\n", p_eng->arg.ctrl.w);  in parse_arg_dedicated()
1134 		printf("speed=0x%1x\n", p_eng->arg.run_speed);  in parse_arg_dedicated()
1140 	return 0;  in parse_arg_dedicated()
1159 	return 0;  in parse_arg_ncsi()
1166 	writel(0, 0x1e620064);  in disable_wdt()
1168 	writel(0, 0x1e78502c);  in disable_wdt()
1191 		if (p_eng->arg.GARPNumCnt != 0)  in setup_data()
1195 	p_eng->run.speed_idx = 0;  in setup_data()
1198 		return (finish_check(p_eng, 0));  in setup_data()
1200 	return 0;			  in setup_data()
1219 	uint32_t wrn_flag_allspeed = 0;  in test_start()
1220 	uint32_t err_flag_allspeed = 0;  in test_start()
1221 	uint32_t des_flag_allspeed = 0;  in test_start()
1222 	uint32_t ncsi_flag_allspeed = 0;  in test_start()
1224 	memset(&p_eng->io.result_history[0][0], 0,  in test_start()
1227 	for (speed = 0; speed < 3; speed++) {  in test_start()
1231 		if (0 == p_eng->run.speed_sel[speed]) {  in test_start()
1239 				if (p_eng->run.speed_sel[0])  in test_start()
1249 				if (0 == p_eng->run.loop_max)  in test_start()
1262 				return (finish_check(p_eng, 0));  in test_start()
1324 						return (finish_check(p_eng, 0));  in test_start()
1344 						p_eng->flg.warn = 0;  in test_start()
1345 						p_eng->flg.error = 0;  in test_start()
1346 						p_eng->flg.desc = 0;  in test_start()
1347 						p_eng->flg.ncsi = 0;  in test_start()
1370 			p_eng->flg.warn = 0;  in test_start()
1371 			p_eng->flg.error = 0;  in test_start()
1372 			p_eng->flg.desc = 0;  in test_start()
1373 			p_eng->flg.ncsi = 0;  in test_start()
1377 			if (p_phy_eng->fp_clr != 0)  in test_start()
1381 		p_eng->run.speed_sel[speed] = 0;  in test_start()
1382 		p_eng->flg.print_en = 0;  in test_start()
1383 	} // End for (speed = 0; speed < 3; speed++)  in test_start()
1390 	return (finish_check(p_eng, 0));  in test_start()
1396 	SCU_WR(0, reg_offset);  in ring_clk()
1397 	SCU_WR((0xf << 2) | BIT(0), reg_offset);  in ring_clk()
1399 	SCU_WR((clk_sel << 2) | BIT(1) | BIT(0), reg_offset);  in ring_clk()
1400 	while ((SCU_RD(reg_offset) & BIT(6)) == 0);  in ring_clk()
1403 	SCU_WR(0, reg_offset);  in ring_clk()
1415 	       p_eng->env.is_new_mdio_reg[0],  in dump_setting()
1420 	       p_eng->env.is_1g_valid[0],  in dump_setting()
1428 	printf("RGMIICK of MAC1/2 = %d Hz\n", ring_clk(0x320, 0xf));  in dump_setting()
1429 	printf("RGMIICK of MAC3/4 = %d Hz\n", ring_clk(0x330, 0x9));  in dump_setting()
1430 	printf("EPLL              = %d Hz\n", ring_clk(0x320, 0x5) * 4);  in dump_setting()
1431 	printf("HCLK              = %d Hz\n", ring_clk(0x330, 0x1));  in dump_setting()
1474 	if (mac_eng.arg.ctrl.b.rmii_50m_out && 0 == mac_eng.run.is_rgmii) {  in mac_test()
1500 	for(int i = 0; i < 3; i++)  in mac_test()
1509 	return 0;  in mac_test()