xes/xpedite550x/ddr.c

1 // SPDX-License-Identifier: GPL-2.0+
4  * Copyright 2007-2008 Freescale Semiconductor, Inc.
20  *     There are traditionally three board-specific SDRAM timing parameters
23  *	       - TIMING_CFG_2 register
25  *		       chip-specific internal delays.
27  *	       - DDR_SDRAM_CLK_CNTL register
30  *	       - TIMING_CFG_2 register
32  *	       Usually only needed with heavy load/very high speed (>DDR2-800)
34  *     ====== XPedite550x DDR3-800 read delay calculations ======
51 			/* DDR3-600/667 */
58 			/* DDR3-800 */
86 			popts->cs_local_opts[i].odt_rd_cfg = 0;  in fsl_ddr_board_options()
87 			popts->cs_local_opts[i].odt_wr_cfg = 0;  in fsl_ddr_board_options()
90 				popts->cs_local_opts[i].odt_rd_cfg = 0;  in fsl_ddr_board_options()
91 				popts->cs_local_opts[i].odt_wr_cfg = 4;  in fsl_ddr_board_options()
93 				popts->cs_local_opts[i].odt_rd_cfg = 3;  in fsl_ddr_board_options()
94 				popts->cs_local_opts[i].odt_wr_cfg = 3;  in fsl_ddr_board_options()
106 		if (ddr_freq >= pbsp->datarate_mhz_low &&  in fsl_ddr_board_options()
107 		    ddr_freq <= pbsp->datarate_mhz_high) {  in fsl_ddr_board_options()
108 			popts->clk_adjust = pbsp->clk_adjust;  in fsl_ddr_board_options()
109 			popts->cpo_override = pbsp->cpo;  in fsl_ddr_board_options()
110 			popts->twot_en = 0;  in fsl_ddr_board_options()
122 	 * Factors to consider for half-strength driver enable:  in fsl_ddr_board_options()
123 	 *	- number of DIMMs installed  in fsl_ddr_board_options()
125 	popts->half_strength_driver_enable = 0;  in fsl_ddr_board_options()
128 	 * Enable on-die termination.  in fsl_ddr_board_options()
129 	 * From the Micron Technical Node TN-41-04, RTT_Nom should typically  in fsl_ddr_board_options()
130 	 * be 30 to 40 ohms, while RTT_WR should be 120 ohms.  Setting RTT_WR  in fsl_ddr_board_options()
133 	popts->rtt_override = 1;  in fsl_ddr_board_options()
134 	popts->rtt_override_value = 3;  in fsl_ddr_board_options()