Lines Matching +full:25 +full:ns
46 * Minimum chip delay (Ch 0): 1.372ns
47 * Maximum chip delay (Ch 0): 2.914ns
48 * Minimum chip delay (Ch 1): 1.220ns
49 * Maximum chip delay (Ch 1): 2.595ns
51 * CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps
57 * = 3.808ns
63 * = 6.240ns
69 * = 3.288ns
75 * = 5.536ns
77 * Ch.0: 3.808ns to 6.240ns additional delay needed (pick 5ns as target)
79 * Ch.1: 3.288ns to 5.536ns additional delay needed (pick 4.4ns as target)
89 * Minimum chip delay (Ch 0): 1.372ns
90 * Maximum chip delay (Ch 0): 2.914ns
91 * Minimum chip delay (Ch 1): 1.220ns
92 * Maximum chip delay (Ch 1): 2.595ns
94 * CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps
100 * = 3.341ns
106 * = 5.673ns
112 * = 2.822ns
118 * = 4.968ns
120 * Ch.0: 3.341ns to 5.673ns additional delay needed (pick 4.5ns as target)
122 * Ch.1: 2.822ns to 4.968ns additional delay needed (pick 3.9ns as target)
133 * Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 = 0.342ns
134 * Ch. 0 8572 to DRAM propagation (CLKs) : 2.3" * 180 = 0.414ns
135 * Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 = 0.126ns
136 * Ch. 1 8572 to DRAM propagation (CLKs ) : 1.47" * 180 = 0.264ns
139 * Ch. 0 0.072ns
140 * Ch. 1 0.138ns
142 * Both of these values are much less than 25% of the clock