27  *   0x30 == 40 Ohm
28  *   0x28 == 48 Ohm
31 #define IMX6DQ_DRIVE_STRENGTH		0x30
32 #define IMX6SDL_DRIVE_STRENGTH		0x28
33 #define IMX6QP_DRIVE_STRENGTH		0x28
44 	.dram_sdba2 = 0x00000000,
74 	.dram_sdba2 = 0x00000000,
97 	.grp_ddr_type = 0x000c0000,
98 	.grp_ddrmode_ctl = 0x00020000,
99 	.grp_ddrpke = 0x00000000,
102 	.grp_ddrmode = 0x00020000,
115 	.grp_ddr_type = 0x000c0000,
116 	.grp_ddrmode_ctl = 0x00020000,
117 	.grp_ddrpke = 0x00000000,
120 	.grp_ddrmode = 0x00020000,
140 	.dram_sdba2 = 0x00000000,
163 	.grp_ddr_type = 0x000c0000,
164 	.grp_ddrmode_ctl = 0x00020000,
165 	.grp_ddrpke = 0x00000000,
168 	.grp_ddrmode = 0x00020000,
208 	.p0_mpwldectrl0 = 0x001f001f,
209 	.p0_mpwldectrl1 = 0x001f001f,
210 	.p1_mpwldectrl0 = 0x001f001f,
211 	.p1_mpwldectrl1 = 0x001f001f,
212 	.p0_mpdgctrl0 = 0x4301030d,
213 	.p0_mpdgctrl1 = 0x03020277,
214 	.p1_mpdgctrl0 = 0x4300030a,
215 	.p1_mpdgctrl1 = 0x02780248,
216 	.p0_mprddlctl = 0x4536393b,
217 	.p1_mprddlctl = 0x36353441,
218 	.p0_mpwrdlctl = 0x41414743,
219 	.p1_mpwrdlctl = 0x462f453f,
225 	.cs1_mirror	= 0,
231 	.rtt_wr		= 0,
233 	.walat		= 0,
235 	.rst_to_cke	= 0x23,
236 	.sde_to_rst	= 0x10,
242 	.p0_mpwldectrl0 = 0x001f001f,
243 	.p0_mpwldectrl1 = 0x001f001f,
244 	.p1_mpwldectrl0 = 0x001f001f,
245 	.p1_mpwldectrl1 = 0x001f001f,
246 	.p0_mpdgctrl0 = 0x420e020e,
247 	.p0_mpdgctrl1 = 0x02000200,
248 	.p1_mpdgctrl0 = 0x42020202,
249 	.p1_mpdgctrl1 = 0x01720172,
250 	.p0_mprddlctl = 0x494c4f4c,
251 	.p1_mprddlctl = 0x4a4c4c49,
252 	.p0_mpwrdlctl = 0x3f3f3133,
253 	.p1_mpwrdlctl = 0x39373f2e,
257 	.p0_mpwldectrl0 = 0x0040003c,
258 	.p0_mpwldectrl1 = 0x0032003e,
259 	.p0_mpdgctrl0 = 0x42350231,
260 	.p0_mpdgctrl1 = 0x021a0218,
261 	.p0_mprddlctl = 0x4b4b4e49,
262 	.p0_mpwrdlctl = 0x3f3f3035,
268 	.cs1_mirror	= 0,
274 	.rtt_wr		= 0,
276 	.walat		= 0,
278 	.rst_to_cke	= 0x23,
279 	.sde_to_rst	= 0x10,
287 	.cs1_mirror	= 0,
293 	.rtt_wr		= 0,
295 	.walat		= 0,
297 	.rst_to_cke	= 0x23,
298 	.sde_to_rst	= 0x10,
307 	writel(0x00C03F3F, &ccm->CCGR0);  in ccgr_init()
308 	writel(0x0030FC03, &ccm->CCGR1);  in ccgr_init()
309 	writel(0x0FFFC000, &ccm->CCGR2);  in ccgr_init()
310 	writel(0x3FF03000, &ccm->CCGR3);  in ccgr_init()
311 	writel(0x00FFF300, &ccm->CCGR4);  in ccgr_init()
312 	writel(0x0F0000C3, &ccm->CCGR5);  in ccgr_init()
313 	writel(0x000003FF, &ccm->CCGR6);  in ccgr_init()
319 	writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);  in spl_dram_init_imx6qp_lpddr3()
321 	writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800);  in spl_dram_init_imx6qp_lpddr3()
323 	writel(0x00060004, MMDC_P0_BASE_ADDR + 0x80c);  in spl_dram_init_imx6qp_lpddr3()
324 	writel(0x000B0004, MMDC_P0_BASE_ADDR + 0x810);  in spl_dram_init_imx6qp_lpddr3()
325 	writel(0x00000004, MMDC_P1_BASE_ADDR + 0x80c);  in spl_dram_init_imx6qp_lpddr3()
326 	writel(0x00000000, MMDC_P1_BASE_ADDR + 0x810);  in spl_dram_init_imx6qp_lpddr3()
329 	 * based on calibration compare of 0x00ffff00  in spl_dram_init_imx6qp_lpddr3()
331 	writel(0x03040314, MMDC_P0_BASE_ADDR + 0x83c);  in spl_dram_init_imx6qp_lpddr3()
332 	writel(0x03080300, MMDC_P0_BASE_ADDR + 0x840);  in spl_dram_init_imx6qp_lpddr3()
333 	writel(0x03000310, MMDC_P1_BASE_ADDR + 0x83c);  in spl_dram_init_imx6qp_lpddr3()
334 	writel(0x0268023C, MMDC_P1_BASE_ADDR + 0x840);  in spl_dram_init_imx6qp_lpddr3()
335 	writel(0x4034363A, MMDC_P0_BASE_ADDR + 0x848);  in spl_dram_init_imx6qp_lpddr3()
336 	writel(0x36302C3C, MMDC_P1_BASE_ADDR + 0x848);  in spl_dram_init_imx6qp_lpddr3()
337 	writel(0x3E3E4046, MMDC_P0_BASE_ADDR + 0x850);  in spl_dram_init_imx6qp_lpddr3()
338 	writel(0x483A4844, MMDC_P1_BASE_ADDR + 0x850);  in spl_dram_init_imx6qp_lpddr3()
339 	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x81c);  in spl_dram_init_imx6qp_lpddr3()
340 	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x820);  in spl_dram_init_imx6qp_lpddr3()
341 	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x824);  in spl_dram_init_imx6qp_lpddr3()
342 	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x828);  in spl_dram_init_imx6qp_lpddr3()
343 	writel(0x33333333, MMDC_P1_BASE_ADDR + 0x81c);  in spl_dram_init_imx6qp_lpddr3()
344 	writel(0x33333333, MMDC_P1_BASE_ADDR + 0x820);  in spl_dram_init_imx6qp_lpddr3()
345 	writel(0x33333333, MMDC_P1_BASE_ADDR + 0x824);  in spl_dram_init_imx6qp_lpddr3()
346 	writel(0x33333333, MMDC_P1_BASE_ADDR + 0x828);  in spl_dram_init_imx6qp_lpddr3()
347 	writel(0x24912489, MMDC_P0_BASE_ADDR + 0x8c0);  in spl_dram_init_imx6qp_lpddr3()
348 	writel(0x24914452, MMDC_P1_BASE_ADDR + 0x8c0);  in spl_dram_init_imx6qp_lpddr3()
349 	writel(0x00000800, MMDC_P0_BASE_ADDR + 0x8b8);  in spl_dram_init_imx6qp_lpddr3()
350 	writel(0x00000800, MMDC_P1_BASE_ADDR + 0x8b8);  in spl_dram_init_imx6qp_lpddr3()
352 	writel(0x00020036, MMDC_P0_BASE_ADDR + 0x004);  in spl_dram_init_imx6qp_lpddr3()
353 	writel(0x09444040, MMDC_P0_BASE_ADDR + 0x008);  in spl_dram_init_imx6qp_lpddr3()
354 	writel(0x898E79A4, MMDC_P0_BASE_ADDR + 0x00c);  in spl_dram_init_imx6qp_lpddr3()
355 	writel(0xDB538F64, MMDC_P0_BASE_ADDR + 0x010);  in spl_dram_init_imx6qp_lpddr3()
356 	writel(0x01FF00DD, MMDC_P0_BASE_ADDR + 0x014);  in spl_dram_init_imx6qp_lpddr3()
357 	writel(0x00011740, MMDC_P0_BASE_ADDR + 0x018);  in spl_dram_init_imx6qp_lpddr3()
358 	writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);  in spl_dram_init_imx6qp_lpddr3()
359 	writel(0x000026D2, MMDC_P0_BASE_ADDR + 0x02c);  in spl_dram_init_imx6qp_lpddr3()
360 	writel(0x008E1023, MMDC_P0_BASE_ADDR + 0x030);  in spl_dram_init_imx6qp_lpddr3()
361 	writel(0x00000047, MMDC_P0_BASE_ADDR + 0x040);  in spl_dram_init_imx6qp_lpddr3()
362 	writel(0x14420000, MMDC_P0_BASE_ADDR + 0x400);  in spl_dram_init_imx6qp_lpddr3()
363 	writel(0x841A0000, MMDC_P0_BASE_ADDR + 0x000);  in spl_dram_init_imx6qp_lpddr3()
364 	writel(0x00400c58, MMDC_P0_BASE_ADDR + 0x890);  in spl_dram_init_imx6qp_lpddr3()
366 	writel(0x00000000, NOC_DDR_BASE_ADDR + 0x008);  in spl_dram_init_imx6qp_lpddr3()
367 	writel(0x2871C39B, NOC_DDR_BASE_ADDR + 0x00c);  in spl_dram_init_imx6qp_lpddr3()
368 	writel(0x000005B4, NOC_DDR_BASE_ADDR + 0x038);  in spl_dram_init_imx6qp_lpddr3()
369 	writel(0x00000040, NOC_DDR_BASE_ADDR + 0x014);  in spl_dram_init_imx6qp_lpddr3()
370 	writel(0x00000020, NOC_DDR_BASE_ADDR + 0x028);  in spl_dram_init_imx6qp_lpddr3()
371 	writel(0x00000020, NOC_DDR_BASE_ADDR + 0x02c);  in spl_dram_init_imx6qp_lpddr3()
372 	writel(0x02088032, MMDC_P0_BASE_ADDR + 0x01c);  in spl_dram_init_imx6qp_lpddr3()
373 	writel(0x00008033, MMDC_P0_BASE_ADDR + 0x01c);  in spl_dram_init_imx6qp_lpddr3()
374 	writel(0x00048031, MMDC_P0_BASE_ADDR + 0x01c);  in spl_dram_init_imx6qp_lpddr3()
375 	writel(0x19308030, MMDC_P0_BASE_ADDR + 0x01c);  in spl_dram_init_imx6qp_lpddr3()
376 	writel(0x04008040, MMDC_P0_BASE_ADDR + 0x01c);  in spl_dram_init_imx6qp_lpddr3()
377 	writel(0x00007800, MMDC_P0_BASE_ADDR + 0x020);  in spl_dram_init_imx6qp_lpddr3()
378 	writel(0x00022227, MMDC_P0_BASE_ADDR + 0x818);  in spl_dram_init_imx6qp_lpddr3()
379 	writel(0x00022227, MMDC_P1_BASE_ADDR + 0x818);  in spl_dram_init_imx6qp_lpddr3()
380 	writel(0x00025576, MMDC_P0_BASE_ADDR + 0x004);  in spl_dram_init_imx6qp_lpddr3()
381 	writel(0x00011006, MMDC_P0_BASE_ADDR + 0x404);  in spl_dram_init_imx6qp_lpddr3()
382 	writel(0x00000000, MMDC_P0_BASE_ADDR + 0x01c);  in spl_dram_init_imx6qp_lpddr3()