1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
37 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;  in fixed_sdram()  local
40 	out_be32(&im->sysconf.ddrlaw[0].bar,  in fixed_sdram()
42 	out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));  in fixed_sdram()
43 	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);  in fixed_sdram()
54 	out_be32(&im->ddr.csbnds[0].csbnds,  in fixed_sdram()
56 		(((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &  in fixed_sdram()
58 	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);  in fixed_sdram()
61 	out_be32(&im->ddr.cs_config[1], 0);  in fixed_sdram()
63 	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);  in fixed_sdram()
64 	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);  in fixed_sdram()
65 	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);  in fixed_sdram()
66 	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);  in fixed_sdram()
67 	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);  in fixed_sdram()
69 	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);  in fixed_sdram()
71 	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);  in fixed_sdram()
72 	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);  in fixed_sdram()
73 	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);  in fixed_sdram()
75 	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);  in fixed_sdram()
79 	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);  in fixed_sdram()
92 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;  in dram_init()  local
93 	volatile fsl_lbc_t *lbc = &im->im_lbc;  in dram_init()
96 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)  in dram_init()
97 		return -1;  in dram_init()
99 	/* DDR SDRAM - Main SODIMM */  in dram_init()
103 	out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);  in dram_init()
104 	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);  in dram_init()
107 	/* return total bus SDRAM size(bytes)  -- DDR */  in dram_init()
108 	gd->ram_size = msize;  in dram_init()
118 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;  in board_early_init_f()  local
119 	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;  in board_early_init_f()
123 	clrbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);  in board_early_init_f()
126 	setbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);  in board_early_init_f()
129 	setbits_be32(&gpio->dir, VE8313_WDT_EN | VE8313_WDT_TRIG);  in board_early_init_f()
137 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;  in hw_watchdog_reset()  local
138 	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;  in hw_watchdog_reset()
141 	reg = in_be32(&gpio->dat);  in hw_watchdog_reset()
143 		clrbits_be32(&gpio->dat, VE8313_WDT_TRIG);  in hw_watchdog_reset()
145 		setbits_be32(&gpio->dat, VE8313_WDT_TRIG);  in hw_watchdog_reset()
175 	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;  in pci_init_board()
176 	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;  in pci_init_board()
180 	setbits_be32(&clk->occr, 0xe0000000);  in pci_init_board()