Lines Matching +full:0 +full:x50000000

11 	/* TLB 0 - for temp stack in cache */
12 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
14 		      MAS3_SW|MAS3_SR, 0,
15 		      0, 0, BOOKE_PAGESZ_4K, 0),
16 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
18 		      MAS3_SW|MAS3_SR, 0,
19 		      0, 0, BOOKE_PAGESZ_4K, 0),
20 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
22 		      MAS3_SW|MAS3_SR, 0,
23 		      0, 0, BOOKE_PAGESZ_4K, 0),
24 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
26 		      MAS3_SW|MAS3_SR, 0,
27 		      0, 0, BOOKE_PAGESZ_4K, 0),
34 	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
38 			0, 0, BOOKE_PAGESZ_1M, 1),
40 	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
42 		      0, 0, BOOKE_PAGESZ_4K, 1),
48 		      0, 1, BOOKE_PAGESZ_16M, 1),
53 		      0, 2, BOOKE_PAGESZ_64K, 1),
56 		      0, 3, BOOKE_PAGESZ_4K, 1),
61 		      0, 4, BOOKE_PAGESZ_1G, 1),
64 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
65 		      CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
67 		      0, 5, BOOKE_PAGESZ_256M, 1),
69 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
70 		      CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
72 		      0, 6, BOOKE_PAGESZ_256M, 1),
77 		      0, 7, BOOKE_PAGESZ_256K, 1),
82 		      MAS3_SW|MAS3_SR, 0,
83 		      0, 9, BOOKE_PAGESZ_1M, 1),
84 	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
85 		      CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
87 		      0, 10, BOOKE_PAGESZ_1M, 1),
91 		      MAS3_SW|MAS3_SR, 0,
92 		      0, 11, BOOKE_PAGESZ_1M, 1),
93 	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
94 		      CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
96 		      0, 12, BOOKE_PAGESZ_1M, 1),
101 		      0, 13, BOOKE_PAGESZ_4M, 1),