1 // SPDX-License-Identifier: GPL-2.0+
44 static long int get_ddr_bank_size(short cs, long *base);
45 static void set_cs_bounds(short cs, ulong base, ulong size);
46 static void set_cs_config(short cs, long config);
53  * Board initialzation after relocation to RAM. Used to detect the number
58 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)  in board_early_init_r()
61 	/* detect the number of Flash banks */  in board_early_init_r()
72 	int cs;  in dram_init()  local
75 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE;  in dram_init()
76 	im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G);  in dram_init()
78 	/* set CS bounds to maximum size */  in dram_init()
79 	for(cs = 0; cs < 4; ++cs) {  in dram_init()
80 		set_cs_bounds(cs,  in dram_init()
81 			CONFIG_SYS_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS),  in dram_init()
84 		set_cs_config(cs, INITIAL_CS_CONFIG);  in dram_init()
93 	im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |  in dram_init()
101 	for(cs = 0; cs < 4; ++cs) {  in dram_init()
102 		debug("\nDetecting Bank%d\n", cs);  in dram_init()
104 		bank_size = get_ddr_bank_size(cs,  in dram_init()
108 		debug("DDR Bank%d size: %ld MiB\n\n", cs, bank_size >> 20);  in dram_init()
114 	gd->ram_size = size;  in dram_init()
131 	if (!(immr->reset.rcwh & HRCWH_PCI_HOST)) {  in checkboard()
138 	if (immr->reset.rcwh & HRCWH_64_BIT_PCI)  in checkboard()
142 	f = gd->pci_clk;  in checkboard()
159  * Detect the number of flash banks (1 or 2). Store it in
235 	debug("Number of flash banks detected: %d\n", cfi_flash_num_flash_banks);  in detect_num_flash_banks()
239 		   (-(total_size) & OR_GPCM_AM));  in detect_num_flash_banks()
247  * Detect the size of a ddr bank. Sets CS bounds and CS config accordingly.
249 static long int get_ddr_bank_size(short cs, long *base)  in get_ddr_bank_size()  argument
252 	 * Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM).  in get_ddr_bank_size()
276 	detected = -1;  in get_ddr_bank_size()
280 		set_cs_config(cs, CSCONFIG_EN | conf[i].col | conf[i].row);  in get_ddr_bank_size()
296 	if(detected == -1){  in get_ddr_bank_size()
297 		/* disable empty cs */  in get_ddr_bank_size()
298 		debug("\nNo valid configurations for CS%d, disabling...\n", cs);  in get_ddr_bank_size()
299 		set_cs_config(cs, 0);  in get_ddr_bank_size()
306 	/* configure cs ro detected params */  in get_ddr_bank_size()
307 	set_cs_config(cs, CSCONFIG_EN | conf[detected].row |  in get_ddr_bank_size()
310 	set_cs_bounds(cs, (long)base, conf[detected].size);  in get_ddr_bank_size()
316  * Sets DDR bank CS bounds.
318 static void set_cs_bounds(short cs, ulong base, ulong size)  in set_cs_bounds()  argument
320 	debug("Setting bounds %08lx, %08lx for cs %d\n", base, size, cs);  in set_cs_bounds()
322 		im->ddr.csbnds[cs].csbnds = 0x00000000;  in set_cs_bounds()
324 		im->ddr.csbnds[cs].csbnds =  in set_cs_bounds()
326 			(((base + size - 1) >> CSBNDS_EA_SHIFT) &  in set_cs_bounds()
333  * Sets DDR banks CS configuration.
334  * config == 0x00000000 disables the CS.
336 static void set_cs_config(short cs, long config)  in set_cs_config()  argument
338 	debug("Setting config %08lx for cs %d\n", config, cs);  in set_cs_config()
339 	im->ddr.cs_config[cs] = config;  in set_cs_config()
348 	im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN |  in set_ddr_config()
353 	im->ddr.timing_cfg_1 =  in set_ddr_config()
363 	im->ddr.timing_cfg_2 =  in set_ddr_config()
369 	im->ddr.sdram_cfg =  in set_ddr_config()
375 	im->ddr.sdram_mode =  in set_ddr_config()
385 	im->ddr.sdram_interval =  in set_ddr_config()
401 	if ((im->sysconf.spridr & SPRIDR_REVID) < 0x200) {  in set_ddr_config()