Lines Matching refs:Set

69 {pmic_i2c, 0xD0, 0x1F}, // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register
70 {pmic_i2c, 0xD1, 0x1F}, // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register
93 {pmic_i2c, 0xF1, 0x03}, // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
94 {pmic_i2c, 0xF1, 0x0B}, // Set Bank 1 ANTIFUSE_EN
102 {pmic_i2c, 0xF2, 0x03}, // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
103 {pmic_i2c, 0xF2, 0x0B}, // Set Bank 2 ANTIFUSE_EN
111 {pmic_i2c, 0xF3, 0x03}, // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
112 {pmic_i2c, 0xF3, 0x0B}, // Set Bank 3 ANTIFUSE_EN
120 {pmic_i2c, 0xF4, 0x03}, // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
121 {pmic_i2c, 0xF4, 0x0B}, // Set Bank 4 ANTIFUSE_EN
129 {pmic_i2c, 0xF5, 0x03}, // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
130 {pmic_i2c, 0xF5, 0x0B}, // Set Bank 5 ANTIFUSE_EN
138 {pmic_i2c, 0xF6, 0x03}, // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
139 {pmic_i2c, 0xF6, 0x0B}, // Set Bank 6 ANTIFUSE_EN
147 {pmic_i2c, 0xF7, 0x03}, // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
148 {pmic_i2c, 0xF7, 0x0B}, // Set Bank 7 ANTIFUSE_EN
156 {pmic_i2c, 0xF8, 0x03}, // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
157 {pmic_i2c, 0xF8, 0x0B}, // Set Bank 8 ANTIFUSE_EN
165 {pmic_i2c, 0xF9, 0x03}, // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
166 {pmic_i2c, 0xF9, 0x0B}, // Set Bank 9 ANTIFUSE_EN
174 {pmic_i2c, 0xFA, 0x03}, // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
175 {pmic_i2c, 0xFA, 0x0B}, // Set Bank 10 ANTIFUSE_EN