Lines Matching +full:0 +full:x00000033
25 #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
27 (MV_USB_PHY_BASE + ((port) << 12) + ((chan) << 6) + 0x8)
29 #define THEADORABLE_GPP_OUT_ENA_LOW 0x00336780
30 #define THEADORABLE_GPP_OUT_ENA_MID 0x00003cf0
31 #define THEADORABLE_GPP_OUT_ENA_HIGH (~(0x0))
33 #define THEADORABLE_GPP_OUT_VAL_LOW 0x2c0c983f
34 #define THEADORABLE_GPP_OUT_VAL_MID 0x0007000c
35 #define THEADORABLE_GPP_OUT_VAL_HIGH 0x00000000
43 #define STM_I2C_ADDR 0x27
48 {0x00001400, 0x7301ca28}, /* DDR SDRAM Configuration Register */
49 {0x00001404, 0x30000800}, /* Dunit Control Low Register */
50 {0x00001408, 0x44149887}, /* DDR SDRAM Timing (Low) Register */
51 {0x0000140C, 0x38d93fc7}, /* DDR SDRAM Timing (High) Register */
52 {0x00001410, 0x1b100001}, /* DDR SDRAM Address Control Register */
53 {0x00001424, 0x0000f3ff}, /* Dunit Control High Register */
54 {0x00001428, 0x000f8830}, /* ODT Timing (Low) Register */
55 {0x0000142C, 0x014c50f4}, /* DDR3 Timing Register */
56 {0x0000147C, 0x0000c671}, /* ODT Timing (High) Register */
58 {0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */
59 {0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */
60 {0x000014A0, 0x00000001}, /* DRAM FIFO Control Register */
61 {0x000014A8, 0x00000101}, /* AXI Control Register */
67 {0x000200e8, 0x3fff0e01},
68 {0x00020184, 0x3fffffe0}, /* Close fast path Window to - 2G */
70 {0x0001504, 0x7fffffe1}, /* CS0 Size */
71 {0x000150C, 0x00000000}, /* CS1 Size */
72 {0x0001514, 0x00000000}, /* CS2 Size */
73 {0x000151C, 0x00000000}, /* CS3 Size */
75 {0x00020220, 0x00000007}, /* Reserved */
77 {0x00001538, 0x00000009}, /* Read Data Sample Delays Register */
78 {0x0000153C, 0x00000009}, /* Read Data Ready Delay Register */
80 {0x000015D0, 0x00000650}, /* MR0 */
81 {0x000015D4, 0x00000044}, /* MR1 */
82 {0x000015D8, 0x00000010}, /* MR2 */
83 {0x000015DC, 0x00000000}, /* MR3 */
84 {0x000015E0, 0x00000001},
85 {0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */
86 {0x000015EC, 0xf800a225}, /* DDR PHY */
89 {0x000014C0, 0x192424c9}, /* DRAM addr and Ctrl Driving Strenght*/
90 {0x000014C4, 0x0aaa24c9}, /* DRAM Data and DQS Driving Strenght */
92 {0x0, 0x0}
96 {"theadorable_1333-667", 0x3, 0x5, 0x0, A0, ddr3_theadorable, NULL},
102 * Lane0 - PCIE0.0 X1 (to WIFI Module)
106 * Lane8-11 - PCIE2.0 X4 (to PEX Switch)
110 { MV_PEX_ROOT_COMPLEX, 0x22200001, 0x00001111,
113 0x0060, serdes_change_m_phy
120 * is used. Values from 0...3 are possible (2 bits).
122 u8 serdes_pex_pulse_width[4] = { 0, 2, 2, 2 };
127 return &board_ddr_modes[0]; in ddr3_get_static_ddr_mode()
132 return &theadorable_serdes_cfg[0]; in board_serdes_cfg_get()
137 /* Bit 0 enables PCI 2.0 link capabilities instead of PCI 1.x */ in board_sat_r_get()
138 return 0x01; in board_sat_r_get()
144 writel(0x00000000, MVEBU_MPP_BASE + 0x00); in board_early_init_f()
145 writel(0x03300000, MVEBU_MPP_BASE + 0x04); in board_early_init_f()
146 writel(0x00000033, MVEBU_MPP_BASE + 0x08); in board_early_init_f()
147 writel(0x00000000, MVEBU_MPP_BASE + 0x0c); in board_early_init_f()
148 writel(0x11110000, MVEBU_MPP_BASE + 0x10); in board_early_init_f()
149 writel(0x00221100, MVEBU_MPP_BASE + 0x14); in board_early_init_f()
150 writel(0x00000000, MVEBU_MPP_BASE + 0x18); in board_early_init_f()
151 writel(0x00000000, MVEBU_MPP_BASE + 0x1c); in board_early_init_f()
152 writel(0x00000000, MVEBU_MPP_BASE + 0x20); in board_early_init_f()
155 writel(THEADORABLE_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); in board_early_init_f()
156 writel(THEADORABLE_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); in board_early_init_f()
157 writel(THEADORABLE_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); in board_early_init_f()
158 writel(THEADORABLE_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); in board_early_init_f()
159 writel(THEADORABLE_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00); in board_early_init_f()
160 writel(THEADORABLE_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04); in board_early_init_f()
162 return 0; in board_early_init_f()
170 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; in board_init()
182 * Set RX Channel Control 0 Register: in board_init()
183 * Tests have shown, that setting the LPF_COEF from 0 (1/8) in board_init()
186 setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 1), 0xc); in board_init()
187 setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 2), 0xc); in board_init()
188 setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 3), 0xc); in board_init()
192 if (ret < 0) in board_init()
194 gpio_direction_output(GPIO_USB0_PWR_ON, 0); in board_init()
196 if (ret < 0) in board_init()
198 gpio_direction_output(GPIO_USB1_PWR_ON, 0); in board_init()
203 return 0; in board_init()
210 return 0; in checkboard()
233 bdf = pci_find_device(PCI_VENDOR_ID_PLX, 0x8619, 0); in board_late_init()
247 i2c_buf[0] = STM_I2C_ADDR << 1; in board_late_init()
248 i2c_buf[1] = 0xc5; /* cmd */ in board_late_init()
249 i2c_buf[2] = 0x01; /* enable */ in board_late_init()
251 i2c_buf[3] = REBOOT_DELAY & 0x00ff; in board_late_init()
252 i2c_buf[4] = (REBOOT_DELAY & 0xff00) >> 8; in board_late_init()
254 i2c_buf[5] = 0x00; in board_late_init()
255 i2c_buf[6] = 0x00; in board_late_init()
256 i2c_buf[7] = crc8(0x72, &i2c_buf[0], 7); in board_late_init()
258 ret = i2c_write(STM_I2C_ADDR, 0, 0, &i2c_buf[1], 7); in board_late_init()
263 do_reset(NULL, 0, 0, NULL); in board_late_init()
273 do_reset(NULL, 0, 0, NULL); in board_late_init()
277 return 0; in board_late_init()
293 printf("Checking for PCIe device: VendorID 0x%04x, DeviceId 0x%04x\n", in do_pcie_test()
300 bdf = pci_find_device(ven_id, dev_id, 0); in do_pcie_test()
309 do_reset(NULL, 0, 0, NULL); in do_pcie_test()
312 return 0; in do_pcie_test()
316 pcie, 3, 0, do_pcie_test,