17 static int sunxi_ahci_phy_init(u8 *reg_base)  in sunxi_ahci_phy_init()  argument
22 	writel(0, reg_base + AHCI_RWCR);  in sunxi_ahci_phy_init()
25 	setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19);  in sunxi_ahci_phy_init()
26 	clrsetbits_le32(reg_base + AHCI_PHYCS0R,  in sunxi_ahci_phy_init()
29 	clrsetbits_le32(reg_base + AHCI_PHYCS1R,  in sunxi_ahci_phy_init()
32 	setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 28) | (0x1 << 15));  in sunxi_ahci_phy_init()
33 	clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19));  in sunxi_ahci_phy_init()
34 	clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20));  in sunxi_ahci_phy_init()
35 	clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5));  in sunxi_ahci_phy_init()
38 	setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19));  in sunxi_ahci_phy_init()
42 		reg_val = readl(reg_base + AHCI_PHYCS0R) & (0x7 << 28);  in sunxi_ahci_phy_init()
52 	setbits_le32(reg_base + AHCI_PHYCS2R, (0x1 << 24));  in sunxi_ahci_phy_init()
56 		reg_val = readl(reg_base + AHCI_PHYCS2R) & (0x1 << 24);  in sunxi_ahci_phy_init()
68 	writel(0x7, reg_base + AHCI_RWCR);  in sunxi_ahci_phy_init()