46 		      &flash_info[0]);  in board_late_init()
51 	return 0;  in board_late_init()
65 	struct nand_chip *nand = &nand_chip[0];  in board_nand_init()
79 	if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {  in board_phy_config()
83 		phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);  in board_phy_config()
85 		/* control data pad skew - devaddr = 0x02, register = 0x04 */  in board_phy_config()
86 		ksz9031_phy_extended_write(phydev, 0x02,  in board_phy_config()
89 					   0x0000);  in board_phy_config()
90 		/* rx data pad skew - devaddr = 0x02, register = 0x05 */  in board_phy_config()
91 		ksz9031_phy_extended_write(phydev, 0x02,  in board_phy_config()
94 					   0x0000);  in board_phy_config()
95 		/* tx data pad skew - devaddr = 0x02, register = 0x05 */  in board_phy_config()
96 		ksz9031_phy_extended_write(phydev, 0x02,  in board_phy_config()
99 					   0x0000);  in board_phy_config()
100 		/* gtx and rx clock pad skew - devaddr = 0x02, reg = 0x08 */  in board_phy_config()
101 		ksz9031_phy_extended_write(phydev, 0x02,  in board_phy_config()
104 					   0x03FF);  in board_phy_config()
110 		phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020);  in board_phy_config()
116 		phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001);  in board_phy_config()
119 		phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);  in board_phy_config()
120 		phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);  in board_phy_config()
123 		phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea);  in board_phy_config()
126 		phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);  in board_phy_config()
129 		phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049);  in board_phy_config()
135 	return 0;  in board_phy_config()
140 	int ret = 0;  in board_eth_init()
143 				  PHY_INTERFACE_MODE_GMII) >= 0)  in board_eth_init()