spear/x600/fpga.c

1 // SPDX-License-Identifier: GPL-2.0+
16  * FPGA program pin configuration on X600:
27  * Set the active-low FPGA reset signal.
38  * Set the FPGA's active-low SelectMap program line to the specified level
50  * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
62 	 * INIT signal state generated via a local state-machine.  in fpga_init_fn()
73  * Test the state of the active-high FPGA DONE pin
80 	 * Wait for Tx-FIFO to become empty before looking for DONE  in fpga_done_fn()
82 	while (!(readl(&ssp->sspsr) & SSPSR_TFE))  in fpga_done_fn()
92  * FPGA pre-configuration function. Just make sure that
98 	debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);  in fpga_pre_config_fn()
154 	 * Wait for Tx-FIFO to become ready  in fpga_wr_fn()
156 	while (!(readl(&ssp->sspsr) & SSPSR_TNF))  in fpga_wr_fn()
160 	writel(data, &ssp->sspdr);  in fpga_wr_fn()
186 	fpga_pgm_fn(false, false, 0);	/* make sure program pin is inactive */  in fpga_serialslave_init()
207 	       &misc->expi_clk_cfg);  in expi_setup()
210 	 * 6 uA, Internal feedback, 1st order, Non-dithered, Sample Parameters,  in expi_setup()
213 	writel((pll2_m << 24) | (pll2_p << 8) | (pll2_n), &misc->pll2_frq);  in expi_setup()
215 	       PLL2_CNTL_RESETN | PLL2_CNTL_LOCK, &misc->pll2_cntl);  in expi_setup()
220 	clrbits_le32(&misc->expi_clk_cfg, EXPI_CLK_CFG_RST);  in expi_setup()
234 	writel(readl(&misc->periph1_clken) | MISC_SSP2ENB | MISC_GPIO4ENB,  in x600_init_fpga()
235 	       &misc->periph1_clken);  in x600_init_fpga()
244 	writel(SSPCR0_DSS_16BITS, &ssp->sspcr0);  in x600_init_fpga()
245 	writel(SSPCR1_SSE, &ssp->sspcr1);  in x600_init_fpga()
254 	writel(2, &ssp->sspcpsr);  in x600_init_fpga()