Lines Matching +full:ddr +full:- +full:backup
6 memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e,
7 and a PCI-X slot, dual mini-DB9 for UART, and dual RJ-45 for eTSEC
10 U-Boot Configuration:
13 The following possible U-Boot configuration targets are available:
26 a base clock of 66MHz. Note that you need both PCI enabled in U-Boot
34 then you should build a U-Boot with a _PCI_33_ config and store this
36 card. [The above discussion assumes that the SW2[1-4] has not been changed
41 and three, but with PCI-e support enabled as well.
43 PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx
44 is shown below for sbc8548_PCI_66_PCIE_config. (Note that PCI-e with
49 BusDevFun VendorId DeviceId Device Class Sub-Class
55 BusDevFun VendorId DeviceId Device Class Sub-Class
60 BusDevFun VendorId DeviceId Device Class Sub-Class
82 1) Remove R314 (RES-R0174-033, 1K, 0603). R314 is located on
83 the back of the PCB behind the DDR SDRAM SODIMM connector.
84 2) Solder RES-R0174-033 (1K, 0603) resistor from R314 pin 2 pad
103 Updating U-Boot with U-Boot:
106 Note that versions of U-Boot up to and including 2009.08 had U-Boot stored
107 at 0xfff8_0000 -> 0xffff_ffff (512k). Currently it is being stored from
108 0xfffa_0000 -> 0xffff_ffff (384k). If you use an old macro/script to
109 update U-Boot with U-Boot and it uses the old address, you will render
114 tftp u-boot.bin
123 you to confirm the U-Boot version that was downloaded, and then confirm
127 have U-Boot in the 8MB flash, tied to /CS0.
131 (as a backup, etc) then the steps will become:
133 tftp u-boot.bin
142 to update the in-use U-Boot image, then (again with CONFIG_SYS_ALT_BOOT
145 tftp u-boot.bin
158 that are relevant to U-Boot, based on the board manual. For the
160 reference manual ERG-00327-001.pdf from www.windriver.com
169 rather inconvenient, U-Boot puts it at 0xec00_0000.
175 ----------------------------------------------------------------
187 JP19 PCI mode PCI PCI-X
192 is jumpered parallel to the LBC-SDRAM, then /CS0 is for the
196 and boot U-Boot from the 64MB SODIMM
204 ------------------------------------------------------------------
224 ----------------------------------------------
231 ----------------------------------------------
232 +/- 0.25% 0 0
233 -0.50% 1 0
234 -0.75% 0 1
243 ------------------------------------------------------------------
244 D13 PCI/PCI-X PCI-X PCI
252 ----------------------------------------------------------------------
255 f800_0000 f8b0_1fff CS5 - EPLD
260 but U-Boot places the flash at either ec00 or fc00 based on JP12.
265 --------------------------------------------------------