1 // SPDX-License-Identifier: GPL-2.0+
3  * sbc8349.c -- WindRiver SBC8349 board support.
4  * Copyright (c) 2006-2007 Wind River Systems, Inc.
33 	return 0;  in board_early_init_f()
42 	u32 msize = 0;  in dram_init()
44 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)  in dram_init()
45 		return -1;  in dram_init()
47 	/* DDR SDRAM - Main SODIMM */  in dram_init()
48 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;  in dram_init()
65 	/* set total bus SDRAM size(bytes)  -- DDR */  in dram_init()
66 	gd->ram_size = msize * 1024 * 1024;  in dram_init()
68 	return 0;  in dram_init()
73  *  fixed sdram init -- doesn't use serial presence detect.
82 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;  in fixed_sdram()
83 	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);  in fixed_sdram()
89 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)  in fixed_sdram()
92 	im->ddr.csbnds[2].csbnds =  in fixed_sdram()
94 		(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>  in fixed_sdram()
96 	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;  in fixed_sdram()
99 	im->ddr.cs_config[0] = 0;  in fixed_sdram()
100 	im->ddr.cs_config[1] = 0;  in fixed_sdram()
101 	im->ddr.cs_config[3] = 0;  in fixed_sdram()
103 	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;  in fixed_sdram()
104 	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;  in fixed_sdram()
106 	im->ddr.sdram_cfg =  in fixed_sdram()
113 	/* for 32-bit mode burst length is 8 */  in fixed_sdram()
114 	im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);  in fixed_sdram()
116 	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;  in fixed_sdram()
118 	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;  in fixed_sdram()
122 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;  in fixed_sdram()
131 	return 0;  in checkboard()
148 	volatile fsl_lbc_t *lbc = &immap->im_lbc;  in sdram_init()
159 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;  in sdram_init()
160 	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;  in sdram_init()
161 	lbc->lsrt = CONFIG_SYS_LBC_LSRT;  in sdram_init()
167 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */  in sdram_init()
169 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */  in sdram_init()
171 	*sdram_addr = 0xff;  in sdram_init()
172 	udelay(100);  in sdram_init()
174 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */  in sdram_init()
177 	*sdram_addr = 0xff;  in sdram_init()
178 	udelay(100);  in sdram_init()
180 	*sdram_addr = 0xff;  in sdram_init()
181 	udelay(100);  in sdram_init()
183 	*sdram_addr = 0xff;  in sdram_init()
184 	udelay(100);  in sdram_init()
186 	*sdram_addr = 0xff;  in sdram_init()
187 	udelay(100);  in sdram_init()
189 	*sdram_addr = 0xff;  in sdram_init()
190 	udelay(100);  in sdram_init()
192 	*sdram_addr = 0xff;  in sdram_init()
193 	udelay(100);  in sdram_init()
195 	*sdram_addr = 0xff;  in sdram_init()
196 	udelay(100);  in sdram_init()
198 	*sdram_addr = 0xff;  in sdram_init()
199 	udelay(100);  in sdram_init()
201 	/* 0x58636733; mode register write operation */  in sdram_init()
202 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;  in sdram_init()
204 	*sdram_addr = 0xff;  in sdram_init()
205 	udelay(100);  in sdram_init()
207 	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */  in sdram_init()
209 	*sdram_addr = 0xff;  in sdram_init()
210 	udelay(100);  in sdram_init()
227 	return 0;  in ft_board_setup()