1 // SPDX-License-Identifier: GPL-2.0+
57 	struct exynos4_power *pwr =  in trats_low_power_mode()  local
62 	writel(0x0, &pwr->arm_core1_configuration);  in trats_low_power_mode()
69 	writel(0xa0c80604, &clk->apll_con0);  in trats_low_power_mode()
76 	writel(0x00000100, &clk->div_cpu0);  in trats_low_power_mode()
78 	/* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */  in trats_low_power_mode()
79 	while (readl(&clk->div_stat_cpu0) & 0x1111111)  in trats_low_power_mode()
87 	writel(0x13113117, &clk->div_dmc0);  in trats_low_power_mode()
89 	/* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */  in trats_low_power_mode()
90 	while (readl(&clk->div_stat_dmc0) & 0x11111111)  in trats_low_power_mode()
94 	writel(0x0, &pwr->xxti_configuration);	/* XXTI */  in trats_low_power_mode()
95 	writel(0x0, &pwr->cam_configuration);	/* CAM */  in trats_low_power_mode()
96 	writel(0x0, &pwr->tv_configuration);    /* TV */  in trats_low_power_mode()
97 	writel(0x0, &pwr->mfc_configuration);   /* MFC */  in trats_low_power_mode()
98 	writel(0x0, &pwr->g3d_configuration);   /* G3D */  in trats_low_power_mode()
99 	writel(0x0, &pwr->gps_configuration);   /* GPS */  in trats_low_power_mode()
100 	writel(0x0, &pwr->gps_alive_configuration);	/* GPS_ALIVE */  in trats_low_power_mode()
103 	writel(0x0, &clk->gate_ip_cam);	/* CAM */  in trats_low_power_mode()
104 	writel(0x0, &clk->gate_ip_tv);          /* TV */  in trats_low_power_mode()
105 	writel(0x0, &clk->gate_ip_mfc);	/* MFC */  in trats_low_power_mode()
106 	writel(0x0, &clk->gate_ip_g3d);	/* G3D */  in trats_low_power_mode()
107 	writel(0x0, &clk->gate_ip_image);	/* IMAGE */  in trats_low_power_mode()
108 	writel(0x0, &clk->gate_ip_gps);	/* GPS */  in trats_low_power_mode()
135 		return -ENODEV;  in exynos_power_init()
141 		return -ENODEV;  in exynos_power_init()
147 		return -ENODEV;  in exynos_power_init()
153 		return -ENODEV;  in exynos_power_init()
156 	p_fg->parent =  p_bat;  in exynos_power_init()
157 	p_chrg->parent = p_bat;  in exynos_power_init()
158 	p_muic->parent = p_bat;  in exynos_power_init()
160 	p_bat->low_power_mode = trats_low_power_mode;  in exynos_power_init()
161 	p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic);  in exynos_power_init()
163 	pb = p_bat->pbat;  in exynos_power_init()
164 	chrg = p_muic->chrg->chrg_type(p_muic);  in exynos_power_init()
167 	if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {  in exynos_power_init()
172 	p_fg->fg->fg_battery_check(p_fg, p_bat);  in exynos_power_init()
174 	if (pb->bat->state == CHARGE && chrg == CHARGER_USB)  in exynos_power_init()
221 	int reg, ret;  in s5pc210_phy_control()  local
223 	ret = pmic_get("max8997-pmic", &dev);  in s5pc210_phy_control()
228 		reg = pmic_reg_read(dev, MAX8997_REG_SAFEOUTCTRL);  in s5pc210_phy_control()
229 		reg |= ENSAFEOUT1;  in s5pc210_phy_control()
230 		ret = pmic_reg_write(dev, MAX8997_REG_SAFEOUTCTRL, reg);  in s5pc210_phy_control()
235 		reg = pmic_reg_read(dev, MAX8997_REG_LDO3CTRL);  in s5pc210_phy_control()
236 		reg |= EN_LDO;  in s5pc210_phy_control()
237 		ret = pmic_reg_write(dev, MAX8997_REG_LDO3CTRL, reg);  in s5pc210_phy_control()
242 		reg = pmic_reg_read(dev, MAX8997_REG_LDO8CTRL);  in s5pc210_phy_control()
243 		reg |= EN_LDO;  in s5pc210_phy_control()
244 		ret = pmic_reg_write(dev, MAX8997_REG_LDO8CTRL, reg);  in s5pc210_phy_control()
250 		reg = pmic_reg_read(dev, MAX8997_REG_LDO8CTRL);  in s5pc210_phy_control()
251 		reg &= DIS_LDO;  in s5pc210_phy_control()
252 		ret = pmic_reg_write(dev, MAX8997_REG_LDO8CTRL, reg);  in s5pc210_phy_control()
257 		reg = pmic_reg_read(dev, MAX8997_REG_LDO3CTRL);  in s5pc210_phy_control()
258 		reg &= DIS_LDO;  in s5pc210_phy_control()
259 		ret = pmic_reg_write(dev, MAX8997_REG_LDO3CTRL, reg);  in s5pc210_phy_control()
264 		reg = pmic_reg_read(dev, MAX8997_REG_SAFEOUTCTRL);  in s5pc210_phy_control()
265 		reg &= ~ENSAFEOUT1;  in s5pc210_phy_control()
266 		ret = pmic_reg_write(dev, MAX8997_REG_SAFEOUTCTRL, reg);  in s5pc210_phy_control()
298 	return !!muic->chrg->chrg_type(muic);  in g_dnl_board_usb_cable_connected()
317 	writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);  in board_clock_init()
318 	writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);  in board_clock_init()
319 	writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);  in board_clock_init()
320 	writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);  in board_clock_init()
322 	writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);  in board_clock_init()
323 	writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);  in board_clock_init()
324 	writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);  in board_clock_init()
325 	writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);  in board_clock_init()
326 	writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);  in board_clock_init()
327 	writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);  in board_clock_init()
328 	writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);  in board_clock_init()
329 	writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);  in board_clock_init()
330 	writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);  in board_clock_init()
331 	writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);  in board_clock_init()
332 	writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);  in board_clock_init()
333 	writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);  in board_clock_init()
335 	writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);  in board_clock_init()
336 	writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);  in board_clock_init()
337 	writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);  in board_clock_init()
338 	writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);  in board_clock_init()
339 	writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);  in board_clock_init()
340 	writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);  in board_clock_init()
341 	writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);  in board_clock_init()
342 	writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);  in board_clock_init()
343 	writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);  in board_clock_init()
344 	writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);  in board_clock_init()
345 	writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);  in board_clock_init()
346 	writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);  in board_clock_init()
348 	writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);  in board_clock_init()
349 	writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);  in board_clock_init()
350 	writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);  in board_clock_init()
351 	writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);  in board_clock_init()
352 	writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);  in board_clock_init()
353 	writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);  in board_clock_init()
354 	writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);  in board_clock_init()
355 	writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);  in board_clock_init()
356 	writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);  in board_clock_init()
357 	writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);  in board_clock_init()
358 	writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);  in board_clock_init()
359 	writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);  in board_clock_init()
364 	struct exynos4_power *pwr =  in board_power_init()  local
368 	writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);  in board_power_init()
371 	writel(0, (unsigned int)&pwr->cam_configuration);  in board_power_init()
372 	writel(0, (unsigned int)&pwr->tv_configuration);  in board_power_init()
373 	writel(0, (unsigned int)&pwr->mfc_configuration);  in board_power_init()
374 	writel(0, (unsigned int)&pwr->g3d_configuration);  in board_power_init()
375 	writel(0, (unsigned int)&pwr->lcd1_configuration);  in board_power_init()
376 	writel(0, (unsigned int)&pwr->gps_configuration);  in board_power_init()
377 	writel(0, (unsigned int)&pwr->gps_alive_configuration);  in board_power_init()
381 	writel(0, (unsigned int)&pwr->arm_core1_configuration);  in board_power_init()
419 		return -ENODEV;  in lcd_power()
431 		return -1;  in lcd_power()
443 		return -ENODEV;  in mipi_power()
455 		return -1;  in mipi_power()