Lines Matching refs:value
24 int value; in onenand_board_init() local
30 value = readl(&clk->gate_d01); in onenand_board_init()
31 value &= ~(1 << 2); /* CLK_ONENANDC */ in onenand_board_init()
32 value |= (1 << 2); in onenand_board_init()
33 writel(value, &clk->gate_d01); in onenand_board_init()
35 value = readl(&clk->src0); in onenand_board_init()
36 value &= ~(1 << 24); /* MUX_1nand: 0 from HCLKD0 */ in onenand_board_init()
37 value &= ~(1 << 20); /* MUX_HREF: 0 from FIN_27M */ in onenand_board_init()
38 writel(value, &clk->src0); in onenand_board_init()
40 value = readl(&clk->div1); in onenand_board_init()
41 value &= ~(3 << 16); /* PCLKD1_RATIO */ in onenand_board_init()
42 value |= (1 << 16); in onenand_board_init()
43 writel(value, &clk->div1); in onenand_board_init()
62 value = readl(&onenand->int_err_mask); in onenand_board_init()
63 value &= ~RDY_ACT; in onenand_board_init()
64 writel(value, &onenand->int_err_mask); in onenand_board_init()