Lines Matching +full:0 +full:x1234
43 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; in pm9263_nand_hw_init()
44 writel(csa, &matrix->csa[0]); in pm9263_nand_hw_init()
82 * 0 - disable in pm9263_macb_hw_init()
85 at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */ in pm9263_macb_hw_init()
93 * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0 in pm9263_macb_hw_init()
98 at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0); in pm9263_macb_hw_init()
99 at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0); in pm9263_macb_hw_init()
100 at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0); in pm9263_macb_hw_init()
125 .vl_lower_margin = 0,
136 at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */ in lcd_disable()
158 writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | in pm9263_lcd_hw_psram_init()
159 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0), in pm9263_lcd_hw_psram_init()
160 &smc->cs[0].setup); in pm9263_lcd_hw_psram_init()
164 &smc->cs[0].pulse); in pm9263_lcd_hw_psram_init()
167 &smc->cs[0].cycle); in pm9263_lcd_hw_psram_init()
170 &smc->cs[0].mode); in pm9263_lcd_hw_psram_init()
175 at91_set_pio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */ in pm9263_lcd_hw_psram_init()
180 writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ in pm9263_lcd_hw_psram_init()
181 writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */ in pm9263_lcd_hw_psram_init()
186 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ in pm9263_lcd_hw_psram_init()
187 /* set RCR; 0x10-async mode,0x90-page mode */ in pm9263_lcd_hw_psram_init()
188 writew(0x90, PSRAM_CTRL_REG); in pm9263_lcd_hw_psram_init()
192 * MT45W2M16B - CRE must be 0 in pm9263_lcd_hw_psram_init()
195 writew(0x1234, PHYS_PSRAM); in pm9263_lcd_hw_psram_init()
196 writew(0x5678, PHYS_PSRAM + 2); in pm9263_lcd_hw_psram_init()
199 if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) { in pm9263_lcd_hw_psram_init()
206 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ in pm9263_lcd_hw_psram_init()
207 /* set RCR;0x10-async mode,0x90-page mode */ in pm9263_lcd_hw_psram_init()
208 writew(0x90, PSRAM_CTRL_REG); in pm9263_lcd_hw_psram_init()
211 writew(0x1234, PHYS_PSRAM); in pm9263_lcd_hw_psram_init()
212 writew(0x5678, PHYS_PSRAM+2); in pm9263_lcd_hw_psram_init()
213 if ((readw(PHYS_PSRAM) != 0x1234) in pm9263_lcd_hw_psram_init()
214 || (readw(PHYS_PSRAM + 2) != 0x5678)) in pm9263_lcd_hw_psram_init()
223 return 0; in pm9263_lcd_hw_psram_init()
229 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */ in pm9263_lcd_hw_init()
230 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ in pm9263_lcd_hw_init()
231 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */ in pm9263_lcd_hw_init()
232 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */ in pm9263_lcd_hw_init()
233 at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */ in pm9263_lcd_hw_init()
234 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */ in pm9263_lcd_hw_init()
235 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */ in pm9263_lcd_hw_init()
236 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */ in pm9263_lcd_hw_init()
237 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */ in pm9263_lcd_hw_init()
238 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */ in pm9263_lcd_hw_init()
239 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */ in pm9263_lcd_hw_init()
240 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */ in pm9263_lcd_hw_init()
241 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */ in pm9263_lcd_hw_init()
242 at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */ in pm9263_lcd_hw_init()
243 at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */ in pm9263_lcd_hw_init()
244 at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */ in pm9263_lcd_hw_init()
245 at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */ in pm9263_lcd_hw_init()
246 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */ in pm9263_lcd_hw_init()
247 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */ in pm9263_lcd_hw_init()
248 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */ in pm9263_lcd_hw_init()
249 at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */ in pm9263_lcd_hw_init()
250 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */ in pm9263_lcd_hw_init()
251 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ in pm9263_lcd_hw_init()
257 at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */ in pm9263_lcd_hw_init()
263 gd->fb_base = (stat == 0) ? PHYS_PSRAM : ATMEL_BASE_SRAM0; in pm9263_lcd_hw_init()
289 dram_size = 0; in lcd_show_board_info()
290 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) in lcd_show_board_info()
293 nand_size = 0; in lcd_show_board_info()
294 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) in lcd_show_board_info()
297 flash_size = 0; in lcd_show_board_info()
298 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) in lcd_show_board_info()
313 return 0; in board_early_init_f()
322 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; in board_init()
336 return 0; in board_init()
344 return 0; in dram_init()
349 gd->bd->bi_dram[0].start = PHYS_SDRAM; in dram_init_banksize()
350 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; in dram_init_banksize()
352 return 0; in dram_init_banksize()
363 int rc = 0; in board_eth_init()
365 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01); in board_eth_init()
390 printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss ); in checkboard()
393 return 0; in checkboard()