1 // SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch-tegra/tegra_i2c.h>
12 /* AS3722-PMIC-specific early init code - get CPU rails up, etc */
16 	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;  in tegra_i2c_ll_write_addr()  local
18 	writel(addr, &reg->cmd_addr0);  in tegra_i2c_ll_write_addr()
19 	writel(config, &reg->cnfg);  in tegra_i2c_ll_write_addr()
24 	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;  in tegra_i2c_ll_write_data()  local
26 	writel(data, &reg->cmd_data1);  in tegra_i2c_ll_write_data()
27 	writel(config, &reg->cnfg);  in tegra_i2c_ll_write_data()
36 	debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);  in pmic_enable_cpu_vdd()
37 	/* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */  in pmic_enable_cpu_vdd()
41 	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.  in pmic_enable_cpu_vdd()
47 	debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);  in pmic_enable_cpu_vdd()
49 	 * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.  in pmic_enable_cpu_vdd()
55 	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.  in pmic_enable_cpu_vdd()
60 	debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);  in pmic_enable_cpu_vdd()
62 	 * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.  in pmic_enable_cpu_vdd()
68 	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.  in pmic_enable_cpu_vdd()
73 	debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);  in pmic_enable_cpu_vdd()
75 	 * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.  in pmic_enable_cpu_vdd()
81 	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.  in pmic_enable_cpu_vdd()
86 	debug("%s: Set VDD_SDMMC to 3.3V via AS3722 reg 0x16/4E\n", __func__);  in pmic_enable_cpu_vdd()
88 	 * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.  in pmic_enable_cpu_vdd()
97 	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.  in pmic_enable_cpu_vdd()