Lines Matching +full:inter +full:- +full:data
1 /* SPDX-License-Identifier: GPL-2.0+ */
3 modified from SH-IPL+g
17 #define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
26 #define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
27 A2: 1-3 A1: 1-3 A0: 0-1 */
28 #define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
29 #define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
30 #define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, .. */
33 #define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */
37 #define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
38 A2: 1-3 A1: 1-3 A0: 0-1 */
39 #define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */
40 #define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */
41 #define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, .. */
120 WCR1_D: .long WCR1_D_VALUE /* Inter-area or turnaround wait states */
122 WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */
124 WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */
126 RTCSR_D: .word 0xA518 /* RTCSR Write Code A5h Data 18h */
129 RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */
140 RFCR_D: .word 0xA400 /* RFCR Write Code A4h Data 00h */