1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/mx6-ddr.h>
13 #include <asm/arch/mx6-pins.h>
16 #include <asm/arch/imx-regs.h>
18 #include <asm/mach-imx/iomux-v3.h>
93 /* MT41K128M16JT-125 (2Gb density) */
111 	writel(0x00C03F3F, &ccm->CCGR0);  in ccgr_init()
112 	writel(0x0030FC3F, &ccm->CCGR1);  in ccgr_init()
113 	writel(0x0FFFCFC0, &ccm->CCGR2);  in ccgr_init()
114 	writel(0x3FF00000, &ccm->CCGR3);  in ccgr_init()
115 	writel(0x00FFF300, &ccm->CCGR4);  in ccgr_init()
116 	writel(0x0F0000C3, &ccm->CCGR5);  in ccgr_init()
117 	writel(0x000003FF, &ccm->CCGR6);  in ccgr_init()
123 	struct mx6_mmdc_calibration calibration = {0};  in spl_dram_print_cal()  local
125 	mmdc_read_calibration(sysinfo, &calibration);  in spl_dram_print_cal()
127 	debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);  in spl_dram_print_cal()
128 	debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);  in spl_dram_print_cal()
129 	debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);  in spl_dram_print_cal()
130 	debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);  in spl_dram_print_cal()
131 	debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);  in spl_dram_print_cal()
132 	debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);  in spl_dram_print_cal()
133 	debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);  in spl_dram_print_cal()
134 	debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);  in spl_dram_print_cal()
135 	debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);  in spl_dram_print_cal()
136 	debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);  in spl_dram_print_cal()
137 	debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);  in spl_dram_print_cal()
138 	debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);  in spl_dram_print_cal()
145 	/* Perform DDR DRAM calibration */  in spl_dram_perform_cal()
149 		printf("DDR: Write level calibration error [%d]\n", ret);  in spl_dram_perform_cal()
155 		printf("DDR: DQS calibration error [%d]\n", ret);  in spl_dram_perform_cal()
166 		/* width of data bus:0=16,1=32,2=64 */  in spl_dram_init()
181 		.pd_fast_exit = 1, /* enable precharge power-down fast exit */  in spl_dram_init()
216 	gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;  in board_mmc_init()
235 	/* UART clocks enabled and gd valid - init serial console */  in board_init_f()
244 	memset(__bss_start, 0, __bss_end - __bss_start);  in board_init_f()
270 	/* Default boot sequence SPI -> MMC */  in board_boot_order()
278 	 * to proper u-boot and perform recovery tasks there.  in board_boot_order()
308 /* Return: 1 - boot to U-Boot. 0 - boot OS (falcon mode) */
311 	/* break into full u-boot on 'c' */  in spl_start_uboot()