kosagi/novena/novena_spl.c

1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/mx6-ddr.h>
13 #include <asm/arch/mx6-pins.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/mach-imx/mxc_i2c.h>
25 #include <asm/arch/mx6-ddr.h>
68 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)  macro
132 	 * Use imx6 internal pull-ups to drive PHY mode pins during PHY reset  in novena_spl_setup_iomux_enet()
133 	 * de-assertion. The intention is to use weak signal drivers (pull-ups)  in novena_spl_setup_iomux_enet()
148 	/* De-assert Ethernet PHY nRST */  in novena_spl_setup_iomux_enet()
194  *  0x30 ... SO-DIMM temp sensor
196  *  0x50 ... SO-DIMM ID
200 		.i2c_mode	= MX6_PAD_EIM_D21__I2C1_SCL | PC,
201 		.gpio_mode	= MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
205 		.i2c_mode	= MX6_PAD_EIM_D28__I2C1_SDA | PC,
206 		.gpio_mode	= MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
219 		.i2c_mode	= MX6_PAD_EIM_EB2__I2C2_SCL | PC,
220 		.gpio_mode	= MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
224 		.i2c_mode	= MX6_PAD_EIM_D16__I2C2_SDA | PC,
225 		.gpio_mode	= MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
238 		.i2c_mode	= MX6_PAD_EIM_D17__I2C3_SCL | PC,
239 		.gpio_mode	= MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
243 		.i2c_mode	= MX6_PAD_EIM_D18__I2C3_SDA | PC,
244 		.gpio_mode	= MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
319 	/* Big SD write-protect and card-detect */  in novena_spl_setup_iomux_sdhc()
342 	/* De-assert the nCS */  in novena_spl_setup_iomux_spi()
414 	/* There is no CD for a microSD card, assume always present. */  in board_mmc_getcd()
433 	/* SDCKE[0:1]: 100k pull-up */
436 	/* SDBA2: pull-up disabled */
438 	/* SDODT[0:1]: 100k pull-up, 40 ohm */
486 	/* write leveling calibration determine */
499 	/* Write Calibration: DQ/DM delay relative to DQS write access */
514 	.walat		= 0,	/* Write additional latency */
541 	writel(0x00C03F3F, &ccm->CCGR0);  in ccgr_init()
542 	writel(0x0030FC03, &ccm->CCGR1);  in ccgr_init()
543 	writel(0x0FFFC000, &ccm->CCGR2);  in ccgr_init()
544 	writel(0x3FF00000, &ccm->CCGR3);  in ccgr_init()
545 	writel(0xFFFFF300, &ccm->CCGR4);  in ccgr_init()
546 	writel(0x0F0000C3, &ccm->CCGR5);  in ccgr_init()
547 	writel(0x000003FF, &ccm->CCGR6);  in ccgr_init()
552  * - we have a stack and a place to store GD, both in SRAM
553  * - no variable global data is available
585 	/* UART clocks enabled and gd valid - init serial console */  in board_init_f()