Lines Matching +full:0 +full:x00100000
16 /* TLB 0 - for temp stack in cache */
17 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
19 MAS3_SW|MAS3_SR, 0,
20 0, 0, BOOKE_PAGESZ_4K, 0),
21 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
23 MAS3_SW|MAS3_SR, 0,
24 0, 0, BOOKE_PAGESZ_4K, 0),
25 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
27 MAS3_SW|MAS3_SR, 0,
28 0, 0, BOOKE_PAGESZ_4K, 0),
29 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
31 MAS3_SW|MAS3_SR, 0,
32 0, 0, BOOKE_PAGESZ_4K, 0),
35 * SRAM is at 0xfff00000, it covered the 0xfffff000.
39 0, 0, BOOKE_PAGESZ_1M, 1),
44 0, 1, BOOKE_PAGESZ_16M, 1),
48 0, 2, BOOKE_PAGESZ_64K, 1),
52 0, 3, BOOKE_PAGESZ_512M, 1),
56 0, 4, BOOKE_PAGESZ_512M, 1),
60 0, 6, BOOKE_PAGESZ_128K, 1),
65 0, 7, BOOKE_PAGESZ_256M, 1),
71 0, 8, BOOKE_PAGESZ_256M, 1),
76 MAS3_SW|MAS3_SR, 0,
77 0, 9, BOOKE_PAGESZ_1M, 1),
78 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
79 CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
81 0, 10, BOOKE_PAGESZ_1M, 1),
85 MAS3_SW|MAS3_SR, 0,
86 0, 11, BOOKE_PAGESZ_1M, 1),
87 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
88 CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
90 0, 12, BOOKE_PAGESZ_1M, 1),
95 0, 13, BOOKE_PAGESZ_4M, 1),
105 0, 16, BOOKE_PAGESZ_32K, 1),