Lines Matching +full:0 +full:x00000033
12 DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
13 # bit 3-0: MPPSel0 2, NF_IO[2]
20 # bit 31-28: MPPSel7 0, GPO[7]
22 DATA 0xFFD10004 0x03303300
24 DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
25 # bit 3-0: MPPSel16 0, GPIO[16]
26 # bit 7-4: MPPSel17 0, GPIO[17]
27 # bit 12-8: MPPSel18 1, NF_IO[0]
29 # bit 19-16: MPPSel20 0, GPIO[20]
30 # bit 23-20: MPPSel21 0, GPIO[21]
31 # bit 27-24: MPPSel22 0, GPIO[22]
32 # bit 31-28: MPPSel23 0, GPIO[23]
34 DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
35 DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
36 DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
38 # NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
42 DATA 0xFFD01400 0x43000400 # SDRAM Configuration Register
43 # bit13-0: 0x400 (DDR2 clks refresh rate)
50 DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
51 # bit 3-0: 0 reserved
52 # bit 4: 0=addr/cmd in smame cycle
53 # bit 5: 0=clk is driven during self refresh, we don't care for APX
54 # bit 6: 0=use recommended falling edge of clk for addr/cmd
55 # bit14: 0=input buffer always powered up
57 # bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0
60 # bit31: 0=no additional STARTBURST delay
62 DATA 0xFFD01408 0x34136552 # DDR Timing (Low) (active cycles value +1)
63 # bit3-0: TRAS lsbs
69 # bit23-21: 0x0
73 DATA 0xFFD0140C 0x00000033 # DDR Timing (High)
74 # bit6-0: TRFC
80 DATA 0xFFD01410 0x0000000D # DDR Address Control
81 # bit1-0: 01, Cs0width=x16
89 # bit16: 0, Cs0AddrSel
90 # bit17: 0, Cs1AddrSel
91 # bit18: 0, Cs2AddrSel
92 # bit19: 0, Cs3AddrSel
93 # bit31-20: 0 required
95 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
96 # bit0: 0, OpenPage enabled
97 # bit31-1: 0 required
99 DATA 0xFFD01418 0x00000000 # DDR Operation
100 # bit3-0: 0x0, DDR cmd
101 # bit31-4: 0 required
103 DATA 0xFFD0141C 0x00000652 # DDR Mode
104 DATA 0xFFD01420 0x00000044 # DDR Extended Mode
105 # bit0: 0, DDR DLL enabled
106 # bit1: 0, DDR drive strenght normal
111 # bit10: 0, differential DQS enabled
112 # bit11: 0, required
113 # bit12: 0, DDR output buffer enabled
114 # bit31-13: 0 required
116 DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
117 # bit2-0: 111, required
120 # bit7 : 0
121 # bit8 : 0 , no sample stage
122 # bit9 : 0 , no half clock cycle addition to dataout
123 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
124 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
126 # bit31-16: 0 required
127 DATA 0xFFD01428 0x00074510
128 DATA 0xFFD0147c 0x00007451
130 DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
131 DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
133 # bit1: 0, Write Protect disabled
136 # bit31-24: 0x07, Size (i.e. 128MB)
138 DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
139 DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
140 DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
142 DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low)
143 # bit3-0: 0, ODT0Rd, MODT[0] asserted during read from DRAM CS0
144 # bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0
146 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
147 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
151 DATA 0xFFD0149C 0x0000FC11 # CPU ODT Control
152 # bit3-0: F, ODT0Rd, Internal ODT asserted during read from DRAM bank0
153 # bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0
157 DATA 0xFFD01480 0x00000001 # DDR Initialization Control
161 DATA 0x0 0x0