Lines Matching refs:im
291 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in fixed_sdram() local
296 out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e)); in fixed_sdram()
297 out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f); in fixed_sdram()
298 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); in fixed_sdram()
299 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); in fixed_sdram()
300 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
301 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
302 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
303 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
304 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); in fixed_sdram()
305 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); in fixed_sdram()
306 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); in fixed_sdram()
307 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); in fixed_sdram()
308 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); in fixed_sdram()
310 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); in fixed_sdram()
323 out_be32(&im->sysconf.ddrlaw[0].ar, in fixed_sdram()
325 out_be32(&im->ddr.csbnds[0].csbnds, in fixed_sdram()
334 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in dram_init() local
337 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) in dram_init()
340 out_be32(&im->sysconf.ddrlaw[0].bar, in dram_init()