Lines Matching full:t1
38 li t1, MALTA_REVISION_CORID_CORE_LV
39 beq t0, t1, _gt64120
42 li t1, MALTA_REVISION_CORID_CORE_FPGA6
43 beq t0, t1, _msc01
65 PTR_LI t1, CKSEG1ADDR(GT_DEF_BASE)
67 sw t0, GT_ISD_OFS(t1)
70 PTR_LI t1, CKSEG1ADDR(MALTA_GT_BASE)
74 sw t0, GT_PCI0IOLD_OFS(t1)
76 sw t0, GT_PCI0IOHD_OFS(t1)
80 sw t0, GT_PCI0M0LD_OFS(t1)
82 sw t0, GT_PCI0M0HD_OFS(t1)
85 sw t0, GT_PCI0M1LD_OFS(t1)
87 sw t0, GT_PCI0M1HD_OFS(t1)
98 li t1, 0x1 << MSC01_PBC_CLKCFG_SHF
99 sw t1, MSC01_PBC_CLKCFG_OFS(t0)
102 li t1, (0x1 << MSC01_PBC_CS0TIM_CDT_SHF) | \
104 sw t1, MSC01_PBC_CS0TIM_OFS(t0)
105 li t1, (0x0 << MSC01_PBC_CS0RW_RDT_SHF) | \
109 sw t1, MSC01_PBC_CS0RW_OFS(t0)
110 lw t1, MSC01_PBC_CS0CFG_OFS(t0)
112 and t1, t2
113 ori t1, (0x0 << MSC01_PBC_CS0CFG_ADM_SHF) | \
116 sw t1, MSC01_PBC_CS0CFG_OFS(t0)
120 li t1, 0x0
122 sw t1, MSC01_BIU_MCBAS1L_OFS(t0)
124 sw t1, MSC01_BIU_MCBAS2L_OFS(t0)
128 li t1, MALTA_MSC01_IP1_BASE
130 sw t1, MSC01_BIU_IP1BAS1L_OFS(t0)
132 sw t1, MSC01_BIU_IP1BAS2L_OFS(t0)
136 li t1, MALTA_MSC01_IP2_BASE1
138 sw t1, MSC01_BIU_IP2BAS1L_OFS(t0)
140 li t1, MALTA_MSC01_IP2_BASE2
142 sw t1, MSC01_BIU_IP2BAS2L_OFS(t0)
146 li t1, MALTA_MSC01_IP3_BASE
148 sw t1, MSC01_BIU_IP3BAS1L_OFS(t0)
150 sw t1, MSC01_BIU_IP3BAS2L_OFS(t0)
155 li t1, MALTA_MSC01_PCIMEM_BASE
158 sw t1, MSC01_PCI_SC2PMBASL_OFS(t0)
163 li t1, MALTA_MSC01_PCIIO_BASE
166 sw t1, MSC01_PCI_SC2PIOBASL_OFS(t0)
171 li t1, -CONFIG_SYS_MEM_SIZE
172 sw t1, MSC01_PCI_BAR0_OFS(t0)
175 sw t1, MSC01_PCI_P2SCMSKL_OFS(t0)
179 li t1, (PCI_VENDOR_ID_MIPS << MSC01_PCI_HEAD0_VENDORID_SHF) | \
181 sw t1, MSC01_PCI_HEAD0_OFS(t0)
184 sw t1, MSC01_PCI_HEAD11_OFS(t0)
187 li t1, (PCI_CLASS_BRIDGE_HOST << MSC01_PCI_HEAD2_CLASS_SHF) | \
189 sw t1, MSC01_PCI_HEAD2_OFS(t0)
206 li t1, (PCI_COMMAND_FAST_BACK | \
211 sw t1, MSC01_PCI_HEAD1_OFS(t0)
215 li t1, (0x1 << MSC01_PCI_SWAP_BAR0_BSWAP_SHF) | \
217 sw t1, MSC01_PCI_SWAP_OFS(t0)
223 lw t1, MSC01_PCI_CFG_OFS(t0)
227 or t1, t1, t2
228 sw t1, MSC01_PCI_CFG_OFS(t0)