Lines Matching +full:pwm +full:- +full:off +full:- +full:delay +full:- +full:ms
1 // SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/mx6-pins.h>
14 #include <asm/mach-imx/mxc_i2c.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/mach-imx/video.h>
29 #include <pwm.h>
71 gd->ram_size = imx_ddr_size(); in dram_init()
207 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1; in board_spi_cs_gpio()
244 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; in board_mmc_getcd()
247 switch (cfg->esdhc_base) { in board_mmc_getcd()
290 return -EINVAL; in board_mmc_init()
314 /* rgmii tx clock delay enable */ in mx6_rgmii_rework()
317 /* enable rgmii tx clock delay */ in mx6_rgmii_rework()
328 if (phydev->drv->config) in board_phy_config()
329 phydev->drv->config(phydev); in board_phy_config()
342 /* backlight PWM brightness control */
369 .bus = -1,
370 .addr = -1,
375 .name = "G121X1-L03",
389 .bus = -1,
416 setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); in enable_videopll()
424 * +----> LDB_DI0_SERIAL_CLK_ROOT in enable_videopll()
426 * +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU 455 / 7 = 65 MHz in enable_videopll()
429 clrsetbits_le32(&ccm->analog_pll_video, in enable_videopll()
435 writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); in enable_videopll()
436 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); in enable_videopll()
438 clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); in enable_videopll()
440 while (timeout--) in enable_videopll()
441 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) in enable_videopll()
447 clrsetbits_le32(&ccm->analog_pll_video, in enable_videopll()
460 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); in setup_display_b850v3()
465 clrsetbits_le32(&mxc_ccm->chsccdr, in setup_display_b850v3()
471 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); in setup_display_b850v3()
485 &iomux->gpr[2]); in setup_display_b850v3()
487 clrbits_le32(&iomux->gpr[3], in setup_display_b850v3()
501 * off for atleast 500ms. The boot time is ~300ms, we need to wait for in setup_display_bx50v3()
502 * an additional 200ms here. Unfortunately we use external PMIC for in setup_display_bx50v3()
508 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); in setup_display_bx50v3()
511 clrsetbits_le32(&mxc_ccm->chsccdr, in setup_display_bx50v3()
517 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); in setup_display_bx50v3()
526 &iomux->gpr[2]); in setup_display_bx50v3()
528 clrsetbits_le32(&iomux->gpr[3], in setup_display_bx50v3()
533 /* backlights off until needed */ in setup_display_bx50v3()
543 * Use always serial for U-Boot console
576 vpd->product_id = data[0]; in vpd_callback()
580 vpd->has |= VPD_HAS_MAC1; in vpd_callback()
581 memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH); in vpd_callback()
584 vpd->has |= VPD_HAS_MAC2; in vpd_callback()
585 memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH); in vpd_callback()
594 int fec_index = -1; in process_vpd()
595 int i210_index = -1; in process_vpd()
597 if (!vpd->is_read) { in process_vpd()
602 switch (vpd->product_id) { in process_vpd()
620 if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1)) in process_vpd()
621 eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1); in process_vpd()
623 if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2)) in process_vpd()
624 eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2); in process_vpd()
666 switch (vpd->product_id) { in set_confidx()
699 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; in board_init()
776 env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60"); in board_late_init()
778 env_set("videoargs", "video=LVDS-1:1024x768@65"); in board_late_init()
789 * Removes the 'eth[0-9]*addr' environment variable with the given index
824 /* We need at least 200ms between power on and backlight on in do_backlight_enable()
828 /* enable backlight PWM 1 */ in do_backlight_enable()