gdsys/a38x/controlcenterdc.c

1 // SPDX-License-Identifier: GPL-2.0+
10 #include <tpm-v1.h>
13 #include <asm-generic/gpio.h>
16 #include "../arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.h"
48  * be used by the DDR3 init code in the SPL U-Boot version to configure
54 	/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
97 	if (!request_gpio_by_name(&gpio, "pca9698@22", 31, "fpga-program-gpio")) {  in board_pex_config()
102 		/* give lunatic PCIe clock some time to stabilize */  in board_pex_config()
110 	if (!request_gpio_by_name(&gpio, "pca9698@22", 19, "fpga-done-gpio")) {  in board_pex_config()
121 	if (!request_gpio_by_name(&gpio, "gpio@18100", 6, "cpu-to-fpga-reset")) {  in board_pex_config()
127 	if (!request_gpio_by_name(&gpio, "pca9698@22", 27, "fpga-ready-gpio")) {  in board_pex_config()
174 	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;  in board_init()
230 	/* reset all FPGA-QSGMII instances */  in ccdc_eth_init()
232 		writel(1 << 31, get_fpga()->qsgmii_port_state[k]);  in ccdc_eth_init()
237 		writel(0, get_fpga()->qsgmii_port_state[k]);  in ccdc_eth_init()
267 			 "/soc/internal-regs/i2c@11000/pca9698@%02x", k);  in board_fix_fdt()