148 /* MT41K64M16JT-125 (1Gb density) */
156 	.pagesz = 2,
162 /* MT41K128M16JT-125 (2Gb density) */
165 	.density = 2,
170 	.pagesz = 2,
176 /* MT41K256M16HA-125 (4Gb density) */
184 	.pagesz = 2,
190 /* MT41K512M16HA-125 (8Gb density) */
198 	.pagesz = 2,
489 		/* width of data bus:0=16,1=32,2=64 */  in spl_dram_init()
491 		/* config for full 4GB range so that get_mem_size() works */  in spl_dram_init()
492 		.cs_density = 32, /* 32Gb per CS */  in spl_dram_init()
498 		.rtt_nom = 2 /*DDR3_RTT_120_OHM*/,	/* RTT_Nom = RZQ/2 */  in spl_dram_init()
527 		debug("1gB density\n");  in spl_dram_init()
529 		/* 1x 2Gb density chip - same calib as 2x 2Gb */  in spl_dram_init()
535 		debug("2gB density\n");  in spl_dram_init()
542 		debug("4gB density\n");  in spl_dram_init()
547 		debug("8gB density\n");  in spl_dram_init()
555 		debug("1gB density\n");  in spl_dram_init()
562 		debug("2gB density\n");  in spl_dram_init()
569 		debug("4gB density\n");  in spl_dram_init()
574 		debug("8gB density\n");  in spl_dram_init()
577 		debug("1gB density\n");  in spl_dram_init()
588 		debug("2gB density\n");  in spl_dram_init()
592 			/* 8xMT41K128M16 (2GiB) fly-by mirrored 2-chipsels */  in spl_dram_init()
594 			debug("2gB density - 2 chipsel\n");  in spl_dram_init()
597 				sysinfo.ncs = 2;  in spl_dram_init()
608 			debug("4gB density\n");  in spl_dram_init()
614 			/* 8xMT41K256M16 (4GiB) fly-by mirrored 2-chipsels */  in spl_dram_init()
616 			debug("4gB density - 2 chipsel\n");  in spl_dram_init()
619 				sysinfo.ncs = 2;  in spl_dram_init()
628 			debug("8gB density\n");  in spl_dram_init()
718 		spl_boot_list[2] = BOOT_DEVICE_UART;  in board_boot_order()