Lines Matching +full:0 +full:x50000000
10 /* TLB 0 - for temp stack in cache */
11 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
13 MAS3_SX|MAS3_SW|MAS3_SR, 0,
14 0, 0, BOOKE_PAGESZ_4K, 0),
15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
17 MAS3_SX|MAS3_SW|MAS3_SR, 0,
18 0, 0, BOOKE_PAGESZ_4K, 0),
19 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
21 MAS3_SX|MAS3_SW|MAS3_SR, 0,
22 0, 0, BOOKE_PAGESZ_4K, 0),
23 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
25 MAS3_SX|MAS3_SW|MAS3_SR, 0,
26 0, 0, BOOKE_PAGESZ_4K, 0),
35 0, 0, BOOKE_PAGESZ_512K, 1),
37 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
39 0, 0, BOOKE_PAGESZ_4K, 1),
45 0, 1, BOOKE_PAGESZ_16M, 1),
51 0, 2, BOOKE_PAGESZ_256M, 1),
57 0, 3, BOOKE_PAGESZ_1G, 1),
60 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
61 CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
63 0, 4, BOOKE_PAGESZ_256M, 1),
65 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
66 CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
68 0, 5, BOOKE_PAGESZ_256M, 1),
73 0, 6, BOOKE_PAGESZ_256K, 1),
78 MAS3_SX|MAS3_SW|MAS3_SR, 0,
79 0, 9, BOOKE_PAGESZ_16M, 1),
80 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
81 CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
83 0, 10, BOOKE_PAGESZ_16M, 1),
87 MAS3_SX|MAS3_SW|MAS3_SR, 0,
88 0, 11, BOOKE_PAGESZ_16M, 1),
89 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
90 CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
92 0, 12, BOOKE_PAGESZ_16M, 1),
99 0, 13, BOOKE_PAGESZ_32M, 1),
109 0, 16, BOOKE_PAGESZ_64K, 1),
114 0, 17, BOOKE_PAGESZ_4K, 1),
119 0, 18, BOOKE_PAGESZ_2G, 1)